Process for improving critical dimension uniformity of integrated circuit arrays
Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.
1. A method for patterning integrated circuit (IC) device arrays, comprising:
forming a repeating pattern of features in a masking layer across a first region of a substrate, the first region including array regions and peripheral regions outside the array regions, the features having top and side surfaces, wherein the features are formed in the array regions and the peripheral regions,
applying a blocking mask over the features in the masking layer, the blocking mask differentiating the array regions of the first region from the peripheral regions of the first region, the blocking mask covering substantially all of the top and side surfaces of a plurality of the features in the peripheral regions, wherein the applying comprises applying the blocking mask to the masking layer to then pattern to open a plurality of array regions within the first region, and to cover peripheral regions within the first region outside the array regions; and
transferring the pattern of features in the array regions into the substrate.
2. The method of claim 1 , wherein the IC device comprises a memory.
3. The method of claim 1 , wherein the IC device comprises a microprocessor.
4. The method of claim 1 , wherein the masking layer comprises a hard mask layer or a spacer layer.
5. The method of claim 1 , wherein forming the repeating pattern of features comprises using photolithography.
6. The method of claim 1 , wherein applying the blocking mask comprises using photolithography.
7. The method of claim 1 , wherein transferring the pattern of features in the array region into the substrate comprises using an etch process.
8. The method of claim 7 , wherein the etch process comprises using a dry etch.
9. The method of claim 7 , wherein the etch process comprises using a plasma etch process.
10. The method of claim 7 , wherein the etch process comprises an anisotropic etch process.
11. The method of claim 1 , wherein forming the repeating pattern of features comprises forming a repeating pattern of pitch-multiplied spacers.
12. The method of claim 11 , wherein forming the repeating pattern of pitch-multiplied spacers comprises:
providing a hard mask layer overlying the substrate;
forming a repeating pattern of features in the hard mask layer;
forming spacers on sidewalls of the hard mask layer; and
removing the hard mask layer, thereby forming the repeating pattern of the pitch-multiplied spacers.
13. The method of claim 12 , wherein forming the spacers comprises:
depositing a blanket layer of a spacer material on exposed surfaces of the hard mask layer and a layer underlying the hard mask layer; and
removing spacer material from horizontal surfaces to leave vertically extending, free standing spacers.
14. The method of claim 1 , wherein forming the repeating pattern of features comprises:
providing a first hard mask layer overlying the substrate and a second hard mask layer overlying the first hard mask layer, the first hard mask layer being formed of a material different from that of the second hard mask layer; and
patterning the second hard mask layer to have the repeating pattern of features.
15. The method of claim 14 , wherein the first hard mask is formed of polysilicon, and wherein the second hard mask is formed of amorphous carbon.
16. The method of claim 1 , wherein applying the blocking mask comprises:
applying the blocking mask to the masking layer to cover a plurality of array regions within the first region and to open peripheral regions within the first region outside the array regions;
removing exposed features in the peripheral regions of the masking layer while the blocking mask covers the plurality of array regions; and
removing the blocking mask after removing the features.
17. The method of claim 1 , wherein transferring the pattern of features in the array regions into the substrate comprises: etching a layer underlying the masking layer through openings of the blocking mask and the masking layer in the array regions; and removing the blocking layer and the masking layer.
18. The method of claim 17 , wherein the layer underlying the masking layer comprises a hard mask layer or the substrate.
19. The method of claim 1 , further comprising: filling cavities in the substrate after transferring the pattern of features in the array regions into the substrate; and planarizing a top surface of the substrate.
20. A method for forming a system, comprising:
forming a repeating pattern of lines in a first layer across a first region of a substrate,
the first region including active regions and inactive regions outside the active regions, the lines having top and side surfaces, wherein the lines are formed in the active regions and the inactive regions;
applying a second layer over the features lines in the first layer, the second layer comprising a blocking mask layer that is patterned to open the active regions and to cover the inactive regions such that substantially all of the top and side surfaces of a plurality of the lines in the inactive regions are covered by the second aver, thereby exposing patterns of lines in the active regions; and
transferring the exposed patterns of lines in the active regions of the first layer into a third layer underlying the first layer.
21. The method of claim 20 , wherein the second layer comprises a blocking photoresist.
22. The method of claim 20 , wherein the first layer comprises a hard mask layer.
23. The method of claim 22 , wherein the hard mask layer comprises amorphous carbon.
24. The method of claim 20 , wherein the first layer comprises a spacer layer.
25. The method of claim 24 , wherein the spacer layer comprises silicon oxide.