Semiconductor device and method for manufacturing the same
A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.
1. A semiconductor device, comprising:
a semiconductor substrate;
a device region disposed at a predetermined location of the semiconductor substrate; and
a shallow trench isolation region that isolates the device region, the shallow trench isolation region including
a trench;
a nitride film liner disposed at an upper portion of a side wall of the trench; and
a thermal oxide film disposed at a lower portion of the side wall of the trench;
wherein a second width of a second portion of the shallow trench isolation region at which second portion the thermal oxide film is disposed is arranged to be wider than a first width of a first portion of the shallow trench isolation region at which first portion a lower end of the nitride film liner is disposed.
2. A semiconductor device, comprising:
a semiconductor substrate;
a shallow trench isolation region disposed at a predetermined location of the semiconductor substrate; and
a first device region and a second device region that are disposed next to each other between which first device region and the second device region the shallow trench isolation region is disposed, the first device region and the second device region including a p-MOSFET and an n-MOSFET, respectively;
wherein the shallow trench isolation region includes
a trench;
a nitride film liner disposed at an upper portion of a first side wall of the trench which first side wall is adjacent to the n-MOSFET when viewed in cross section across a channel direction; and
a thermal oxide film disposed at a lower portion of the trench; wherein
the nitride film liner is not disposed at an upper portion of a second side wall of the trench which second side wall is adjacent to the p-MOSFET when viewed in cross section across the channel direction.
3. The semiconductor device as claimed in claim 2 , wherein
the thermal oxide film is arranged to extend from the lower portion of the trench to an upper end of the second trench side wall.
4. The semiconductor device as claimed in claim 2 , wherein
the nitride film liner is not disposed at a third side wall of the trench which third side wall is adjacent to the p-MOSFET when viewed in cross section across a direction perpendicular to the channel direction.
5. The semiconductor device as claimed in claim 2 , wherein
the thermal oxide film is arranged on a third side wall of the trench which third side wall is adjacent to the p-MOSFET when viewed in cross section across a direction perpendicular to the channel direction.
6. The semiconductor device as claimed in claim 2 , wherein
the nitride film liner is arranged on an upper portion of a third side wall of the trench which third side wall is adjacent to the p-MOSFET when viewed in cross section across a direction perpendicular to the channel direction; and
the thermal oxide film is arranged on a lower portion of the third side wall.
7. The semiconductor device as claimed in claim 2 , wherein
the shallow trench isolation region further includes an oxide film liner that is disposed at a periphery of the nitride film liner.
8. The semiconductor device as claimed in claim 2 , wherein
an isolation width of a portion of the shallow trench isolation region at which portion the thermal oxide film is disposed is arranged to be greater than an exposure positioning deviation margin for well implantation.
9. The semiconductor device as claimed in claim 2 , wherein
the shallow trench isolation region further includes an oxide film that is employed to fill in the trench.
10. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first trench having a predetermined depth at a predetermined location of a semiconductor substrate;
forming a nitride film over an inner side of the first trench;
removing the nitride film from a bottom portion of the first trench and exposing the semiconductor substrate through the bottom portion while preserving the nitride film arranged at an upper portion of the first trench;
etching a second trench from the bottom portion of the first trench after removing the nitride film; and
performing thermal oxidation on the exposed bottom portion and forming a thermal oxide film extending from a lower end of the nitride film toward the semiconductor substrate;
wherein the thermal oxidation is performed on the second trench and the thermal oxide film extending from the lower end of the nitride film toward the semiconductor substrate is arranged at the second trench.
11. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first trench having a predetermined depth at a predetermined location of a semiconductor substrate;
configuring the first trench to isolate a p-MOSFET region and an n-MOSFET region;
forming a nitride film over an inner side of the first trench;
removing the nitride film from a bottom portion of the first trench and exposing the semiconductor substrate through the bottom portion while preserving the nitride film arranged at an upper portion of the first trench;
after removing the nitride film from the bottom portion of the first trench, preserving the nitride film arranged at a first side wall of the first trench which first side wall is adjacent to the n-MOSFET region when viewed in cross section across a channel direction, and removing the nitride film from a second side wall of the first trench which second side wall is adjacent to the p-MOSFET when viewed in cross section across the channel direction; and
performing thermal oxidation on the bottom portion and the second side wall, and forming a thermal oxide film extending from a lower end of the nitride film arranged at the first side wall and the upper end of the second side wall toward the semiconductor substrate.
12. The method as claimed in claim 11 , further comprising the step of:
etching a second trench from the bottom portion of the first trench;
wherein the thermal oxidation is performed on a third side wall of the second trench which third side wall is adjacent to the n-MOSFET when viewed in cross section across the channel direction, a fourth side wall of the second trench which fourth side wall is adjacent to the p-MOSFET when viewed in cross section across the channel direction, and the second side wall of the first trench; and
the thermal oxide film extending from the lower end of the nitride film toward the semiconductor substrate is arranged on the second side wall, the third side wall, and the fourth side wall.
13. The method as claimed in claim 11 , wherein
the step of removing the nitride film includes removing the nitride film from a fifth side wall of the first trench which fifth side wall is adjacent to the p-MOSFET when viewed in cross section across a direction perpendicular to the channel direction.
14. The method as claimed in claim 13 , wherein
the step of forming the thermal oxide film includes arranging the thermal oxide film over the fifth side wall that is adjacent to the p-MOSFET when viewed in cross section across the direction perpendicular to the channel direction.
15. The method as claimed in claim 13 , wherein
the step of removing the nitride film involves using an n-well implant mask.
16. The method as claimed in claim 11 , wherein
in the step of removing the nitride film, the nitride film is arranged to remain on a fifth side wall of the first trench which fifth side wall is adjacent to the p-MOSFET when viewed in cross section across a direction perpendicular to the channel direction.
17. The method as claimed in claim 16 , wherein
the step of removing the nitride film involves using a combination of an n-well implant mask and an enlarged gate mask.
18. The method as claimed in claim 11 , further comprising the step of:
performing resist exposure for well implantation after filling in the first trench with an implant material;
wherein an isolation width of a portion of the shallow trench isolation region at which portion the thermal oxide film is disposed is arranged to be greater than an exposure positioning deviation margin for the resist exposure step.
19. The method as claimed in claim 11 , wherein
the thermal oxidation is realized at a temperature of 800-1000° C. through at least one of wet oxidation and dry oxidation.