Atomic layer deposition of Dy doped HfO
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO 2 ) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function.
1. A method comprising:
forming a dielectric layer containing at least one hafnium oxide layer and at least one dysprosium oxide layer by reaction sequence atomic layer deposition; and
forming a conductive metal layer on the dielectric layer;
wherein the method further includes:
forming metallization lines in the metal layer to electrically connect to a device in the integrated circuit; and
annealing the device in a H 2 ambient after forming the metallization lines.
2. The method of claim 1 , wherein the method includes forming the dielectric layer as a gate insulator having a portion of the metal layer as a gate of a transistor in the integrated circuit.
3. The method of claim 2 , wherein the method includes forming the dielectric layer as a gate insulator in a CMOS transistor in the integrated circuit.
4. The method of claim 2 , wherein the method includes forming the metal layer as an electrode of a capacitor and forming the dielectric layer as a dielectric of the capacitor.
5. A method comprising:
forming a memory array in a substrate including:
forming a dielectric layer containing a dysprosium oxide doped hafnium oxide layer in an integrated circuit including forming the dielectric layer by atomic layer deposition;
depositing a conductive layer contacting the dielectric layer; and
forming an address decoder in the substrate, the address decoder coupled to the memory array.
6. The method of claim 5 , wherein the method is a method of forming a flash memory device, and forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator having the conductive layer as a gate of a transistor in the flash memory device.
7. The method of claim 5 , wherein the method is a method of forming a memory device including forming the conductive layer as an electrode of a capacitor and forming the dielectric layer as a dielectric of the capacitor in the memory device.
8. The method of claim 5 , wherein the method further includes:
forming metallization lines in the memory array; and
annealing the device in a H 2 ambient after forming the metallization lines.
9. The method of claim 5 , wherein depositing a conductive layer includes depositing by sputtering.
10. The method of claim 5 , wherein the dielectric layer is formed at a temperature of less than 300° C.
11. A method comprising:
providing a controller;
coupling an integrated circuit to the controller, wherein the integrated circuit includes a dielectric layer contacting a conductive layer, the dielectric layer comprising a dysprosium oxide doped and hafnium oxide, wherein forming the dielectric layer contacting the conductive layer includes:
forming the nanolaminate dielectric layer by atomic layer deposition; and
depositing the conductive layer such that the conductive layer contacts the dielectric layer.
12. The method of claim 11 , wherein coupling an integrated circuit to the controller includes coupling a memory device formed as the integrated circuit.
13. The method of claim 11 , wherein providing a controller includes providing a processor.
14. The method of claim 11 , wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit formed as the integrated circuit having the dielectric layer contacting the conductive layer.
15. The method of claim 11 , wherein the method is a method of forming an information handling system.
16. An electronic device comprising:
an amorphous dielectric layer containing an atomic layer deposited dielectric layer of dysprosium oxide doped hafnium oxide in an integrated circuit; and
a conductive layer contacting the dielectric layer.
17. The electronic device of claim 16 wherein the dysprosium comprises 10% of the dielectric film.
18. The electronic device of claim 16 , wherein the electronic device includes a memory having the dielectric as a gate insulator in a transistor device.
19. The electronic device of claim 18 , wherein the gate insulator in the memory device is an inter-gate insulator in a flash memory device.
20. The electronic device of claim 16 , wherein the electronic device includes a transistor in the integrated circuit, the transistor having the dielectric layer as a gate insulator and the conductive layer as a gate in the transistor.
21. The electronic device of claim 16 , wherein the electronic device includes a CMOS transistor in the integrated circuit, the CMOS transistor having the dielectric layer as a gate insulator and the conductive layer as a gate.
22. The electronic device of claim 16 , wherein the electronic device includes a capacitor having the dielectric layer as a dielectric material between two electrodes in the capacitor, and the conductive layer as at least one of the two electrodes.
23. The electronic device of claim 16 , further comprising:
a controller coupled to the electronic device, wherein the electronic device includes:
a dielectric layer comprising an atomic layer deposited dielectric layers of dysprosium oxide doped hafnium oxide in an integrated circuit; and
a conductive layer contacting the dielectric layer.
24. The electronic device of claim 23 , wherein the electronic device includes a memory.