Electronic network circuit with dissymmetrical differential pairs
The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T 1 , T 2 ; T 3 , T 4 ) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T 2 , T 4 ) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T 1 , T 3 ) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.
1. An analog-to-digital converter, comprising:
a dual differential pair each composed of two identical single differential pairs of two transistors, the dual differential pair receiving a differential input signal which is the difference between a first and a second variable voltage each applied respectively to a first respective transistor of each single pair, and further receiving a fixed reference signal applied to a second respective transistor of each single differential pair, each single pair being powered by a respective current source connected to emitters of the two transistors of the pair in such a way that the current from the source is shared between the emitters of the pair's transistors, wherein each of the two differential pairs, the transistor that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor that receives a variable voltage at its base.
2. The analog-to-digital converter as claimed in claim 1 , wherein the transistor that receives a fixed reference voltage has an effective emitter surface double the other.
3. The analog-to-digital converter as claimed in claim 2 , wherein the transistor that receives a fixed reference voltage consists of two transistors in parallel, identical to the transistor that receives the variable voltage.
4. The analog-to-digital converter as claimed in claim 1 , wherein the fixed reference signal is a differential signal, which is the difference between two reference voltages (Vrefp, Vrefn) applied respectively to the base of the second transistor of each of the pairs.
5. An application of the integrated circuit as claimed in claim 1 to an analog signal folding circuit with multiple differential pairs.
6. An application of the integrated circuit as claimed in claim 1 to a flash type analog-to-digital converter using dual differential pair comparators.
7. The analog-to-digital converter as claimed in claim 2 , wherein the fixed reference signal is a differential signal, which is the difference between two reference voltages (Vrefp, Vrefn) applied respectively to the base of the second transistor of each of the pairs.
8. The analog-to-digital converter as claimed in claim 3 , wherein the fixed reference signal is a differential signal, which is the difference between two reference voltages (Vrefp, Vrefn) applied respectively to the base of the second transistor of each of the pairs.
9. An application of the integrated circuit as claimed in claim 2 to an analog signal folding circuit with multiple differential pairs.
10. An application of the integrated circuit as claimed in claim 3 to an analog signal folding circuit with multiple differential pairs.
11. An application of the integrated circuit as claimed in claim 4 to an analog signal folding circuit with multiple differential pairs.
12. An application of the integrated circuit as claimed in claim 2 to a flash type analog-to-digital converter using dual differential pair comparators.
13. An application of the integrated circuit as claimed in claim 3 to a flash type analog-to-digital converter using dual differential pair comparators.
14. An application of the integrated circuit as claimed in claim 4 to a flash type analog-to-digital converter using dual differential pair comparators.