MOSFET fuse programmed by electromigration
View Patent ↗A one-time programmable field effect transistor (FET) e-fuse has a silicided gate connected to the drain while the source is grounded. A voltage stimulus applied to the drain forces current to flow through the channel coupling the drain to the source. The magnitude of the current exceeding the threshold current density initiates electromigration of the source/drain silicide into the channel region, such that the source/drain of the FET is shorted to the substrate after programming. Under these constraints, the fuse device conducts current even when the transistor is in the off-state. The MOSFET e-fuse preferably uses a minimum channel length NFET/PFET and scales down its dimensions to conform to those allowed by the technology.
1. A fuse, comprising:
a field effect (FET) transistor having a silicided gate, silicided source and silicided drain, wherein said source and drain are coupled to each other by a silicided channel; and
a voltage stimulus applied to said drain, with said source grounded and said gate connected to said drain, said applied voltage inducing electromigration of nitride silicide (NiSi) in said silicided channel by current flowing through said silicided channel.
2. The FET fuse as recited in claim 1 , wherein said FET is a PFET or an NFET device.
3. The FET fuse as recited in claim 1 , wherein a current through said channel exceeds a threshold current density that initiates said electromigration between said source and drain through said channel.
4. The FET fuse as recited in claim 1 , wherein said fuse is formed in a substrate.
5. The FET fuse as recited in claim 4 , wherein a junction breakdown between said drain and said substrate causes a short of the silicide.
6. The FET fuse as recited in claim 1 , wherein sensing means detect said current flowing from said drain to said source through said channel when programming said FET fuse.
7. The FET fuse as recited in claim 6 , wherein said sensing means utilize a reverse biased junction current from said drain to said substrate to program or deprogram said FET fuse.
8. The FET fuse as recited in claim 1 , wherein said fuse is provided with a minimum channel that can be resolved by lithography.
9. The FET fuse as recited in claim 7 , wherein said minimum channel length is 65 nm.
10. The FET fuse as recited in claim 9 , wherein the channel having said minimum length precludes forming a hot spot in said channel when said electromigration is induced under said applied voltage conditions.
11. The FET fuse as recited in claim 10 , wherein said applied voltage ranges from 4 to 5V for an NFET fuse.
12. The FET fuse as recited in claim 9 , wherein said applied voltage ranges from −5 to −10V for a PFET fuse.
13. The FET fuse as recited in claim 11 , wherein said applied voltage has a duration ranging from 5 μsec to 200 μsec.
14. An electrical fuse device integral to a substrate comprising:
a field effect (FET) transistor in said substrate having a silicided gate, silicided source and silicided drain, wherein said source and drain are coupled to each other by a silicided channel; and
a voltage stimulus is applied to said silicided drain, with said silicided source and said silicided gate grounded, said applied voltage inducing electromigration of nitride silicide (NiSi) in said silicided channel by current flowing through said silicided channel.