Wafer bonding of thinned electronic materials and circuits to high performance substrates
View Patent ↗A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.
1. A circuit comprising:
a substrate;
wherein the substrate is microwave insulating; and
a wafer;
wherein the wafer has a front surface comprising a microwave device and more than one independent circuits; and
wherein the wafer has a back surface directly contacted and bonded to the substrate by direct wafer bonding with atom-to-atom bonding with hydrogen or covalent bonds between atoms on the wafer and atoms on the substrate.
2. The circuit of claim 1 , wherein the wafer is at most about 50 microns thick.
3. The circuit of claim 1 , wherein the wafer is a silicon-on-insulator wafer.
4. The circuit of claim 1 , wherein the substrate has a thermal conductivity higher than the thermal conductivity of the wafer.
5. The circuit of claim 1 , wherein the substrate has a thermal conductivity of at least about 150 W/mK.
6. The circuit of claim 1 , wherein the substrate has a resistivity higher than the resistivity of the wafer.
7. The circuit of claim 1 , wherein the substrate has a resistivity of at least about 3000 ohm-cm.
8. The circuit of claim 1 , wherein the substrate is optically transparent.
9. The circuit of claim 1 , wherein the substrate is an Au, Ag, or Li doped silicon substrate.
10. The circuit of claim 1 , wherein the substrate is selected from the group consisting of a composite single-crystal substrate, a composite polycrystalline layer on a single crystal substrate, non-single crystal substrate, and a single-crystal substrate.
11. The circuit of claim 1 , wherein the wafer is at most about 20 μm thick.
12. The circuit of claim 1 , wherein the wafer is at most about 500 nm thick.
13. The circuit of claim 1 , wherein the substrate is semi-insulating.
14. The circuit of claim 1 , wherein the substrate is a gold-doped silicon substrate.