Gas dielectric structure forming methods

1. A method of forming a gas dielectric structure for a semiconductor structure, the method comprising:

forming an opening for semiconductor structure in a dielectric layer on a substrate, wherein the opening includes both a wiring opening and a via opening, wherein the via provides a vertical connection to an interconnect line;

depositing a non-conductive liner, wherein the non-conductive liner includes one of the group consisting of: silicon nitride (Si 3 N 4 ) and silicon dioxide (SiO 2 );

after depositing the non-conductive liner, depositing a sacrificial layer over the opening such that the sacrificial layer fails to substantially fill the opening;

performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening after depositing the sacrificial layer;

depositing a conductive liner over the opening after performing the directional etch;

depositing a metal in the opening after depositing the conductive liner to form a wire and a contact via;

planarizing the metal and the conductive liner after depositing the metal;

removing the sacrificial layer sidewall using a dry etching process, after the metal and the conductive liner are planarized, forming a void, wherein the void extends along a side of the contact via and the wire; and

depositing a cap layer over the void to form the gas dielectric structure.

2. The method of claim 1 , wherein the forming step includes performing a dual damascene process.

3. The method of claim 1 , wherein the forming step includes depositing a hard mask, patterning the hard mask and etching the hard mask.

4. The method of claim 1 , wherein the conductive liner includes at least one of the group consisting of: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) and niobium (Nb).

5. The method of claim 1 , wherein the sacrificial layer includes one of the group consisting of: aluminum (Al) and silicon dioxide (SiO 2 ).

6. A method of forming a gas dielectric structure for a semiconductor structure, the method comprising:

performing a dual damascene process to form an opening including both a wiring opening and a via opening in a dielectric layer on a substrate, wherein the via provides a vertical connection to an interconnect line;

depositing a non-conductive liner, wherein the non-conductive liner includes one of the group consisting of: silicon nitride (Si 3 N 4 ) and silicon dioxide (SiO 2 );

after depositing the non-conductive liner, depositing a sacrificial layer over the opening;

performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall wherein the directional etching removes the sacrificial layer only from substantially horizontal surfaces;

depositing a conductive liner over the opening after performing the directional etch;

depositing a metal in the opening after depositing the conductive liner to form a wire and a contact via;

planarizing the metal and the conductive liner after depositing the metal;

removing the sacrificial layer sidewall using a dry etching process, after the metal and the conductive liner are planarized, forming a void, wherein the void extends along a side of the contact via; and

depositing a cap layer over the void to form the gas dielectric structure.

7. The method of claim 6 , wherein the forming step includes depositing a hard mask, patterning the hard mask and etching the hard mask.

8. The method of claim 6 , wherein the conductive liner includes at least one of the group consisting of: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) and niobium (Nb).

9. The method of claim 6 , wherein the sacrificial layer includes one of the group consisting of: aluminum (Al) and silicon dioxide (SiO 2 ).

10. A method of forming a gas dielectric structure for a semiconductor structure, the method comprising:

performing a via-first dual damascene process to form an opening including both a wiring opening and a via opening in a dielectric layer on a substrate, wherein the via provides a vertical connection between to an interconnect line;

depositing a non-conductive liner, wherein the non-conductive liner includes one of the group consisting of: silicon nitride (Si 3 N 4 ) and silicon dioxide (SiO 2 );

after depositing the non-conductive liner, depositing a sacrificial layer over the opening such that the sacrificial layer fails to substantially fill the opening;

performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall, wherein the directional etching removes the sacrificial layer only from substantially horizontal surfaces;

depositing a conductive liner over the opening after performing the directional etch;

depositing a metal in the opening after depositing the conductive liner to form a wire and a contact via;

planarizing the metal and the conductive liner after depositing the metal;

removing the sacrificial layer sidewall using a dry etching process, after the metal and conductive liner are planarized, forming a void that extends along a side of the contact via; and

depositing a cap layer over the void to form the gas dielectric structure.

11. The method of claim 10 , wherein the conductive liner includes one of the group consisting of: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titantium nitride (TiN), tungsten (W) and niobium (Nb).

12. The method of claim 10 , wherein the sacrificial layer includes one of the group consisting of: aluminum (Al) and silicon dioxide (SiO 2 ).