Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
1. A method for fabricating an integrated circuit, comprising:
providing a first mandrel over a substrate, the first mandrel having a first width;
providing a second mandrel substantially over the first mandrel, the second mandrel having a second width smaller than the first width;
providing a layer of spacer material on the first and second mandrels;
subjecting the layer of spacer material to a spacer etch, wherein the spacer etch simultaneously forms spacers on sidewalls of the first and second mandrels;
selectively removing at least portions of the mandrels relative to the spacers to form a spacer pattern defined by the spacers; and
processing the substrate through a mask defined by the spacer pattern.
2. The method of claim 1 , wherein processing comprises etching to transfer the spacer pattern to the substrate.
3. The method of claim 2 , further comprising transferring the spacer pattern to a lower hard mask layer and removing the spacers prior to processing.
4. The method of claim 3 , wherein the substrate comprises an upper interlevel dielectric layer and processing through the mask forms damascene trenches.
5. The method of claim 4 , wherein the spacer pattern comprises elongated lines with connecting loop ends, and the method further comprises blocking the loop ends prior to processing.
6. The method of claim 3 , wherein providing the first mandrel over the substrate comprises providing the first mandrel over a conductor.
7. The method of claim 6 , wherein the spacer pattern comprises elongated lines with connecting loop ends, and the method further comprises removing the loop ends prior to processing.
8. The method of claim 1 , wherein providing the second mandrel comprises providing the second mandrel extending parallel to the first mandrel.
9. The method of claim 1 , wherein providing the second mandrel comprises providing the second mandrel centered with respect to the first mandrel.
10. The method of claim 1 , wherein simultaneously forming the spacers provides the spacers with a third width that is smaller than the first width.
11. The method of claim 1 , wherein providing the second mandrel comprises using photolithography with a resolution limit greater than about 200 nm.
12. The method of claim 1 , further comprising providing a third mandrel on the second mandrel, the third mandrel having a third width.
13. The method of claim 12 , wherein providing the third mandrel comprises providing the third mandrel having the third width smaller than the second width.
14. The method of claim 13 , wherein providing the third mandrel comprises providing the third mandrel centered with respect to the second mandrel.
15. The method of claim 1 , wherein selectively removing comprises removing portions of the first mandrel.
16. The method of claim 1 , wherein selectively removing comprises leaving portions of the first mandrel directly below spacers on the sidewalls of the second mandrel.
17. The method of claim 1 , wherein providing the layer of spacer material comprises blanket depositing spacer material on surfaces of the substrate.
18. The method of claim 1 , wherein simultaneously forming spacers comprises providing spacers having a width less than or equal to about one half times the first width minus one half times the second width.