Substrate and process for semiconductor flip chip package
View Patent ↗A semiconductor package structure for flip chip package includes at least a patterned circuit layer and an insulating layer alternately stacking up each other. The patterned layer includes a plurality of bump pads, and the insulating layer includes a plurality of etching holes. The etching holes and the bump pads are aligned, such that the bump pads are exposed through the etching holes. A plurality of bumps is disposed on the active surface of the chip, which can be obtained by stud bumping. The etching holes are filled with solder paste, and the bumps of the chips penetrate into the solder filled etching holes. Vibration obtained by mechanical equipment, or ultrasonic equipment can be applied to assist the alignment of the bumps to the corresponding bump pads. A reflow process is applied to collapse the solder paste that fills the etching holes to form electrical connection between the bumps and bump pads.
1. A semiconductor electronic package, comprising:
a circuit chip having an active surface;
a plurality of solder bumps disposed on the active surface;
a solder paste; and
a substrate, including:
a first patterned conductive circuit layer comprising a plurality of solder bump pads; and
a first insulating layer covering the first patterned conductive circuit layer and defining a plurality of holes exposing the solder bump pads, wherein inside walls of the holes are conductive;
wherein:
the solder paste is disposed inside the holes;
the circuit chip is positioned with the active surface facing the holes in the first insulating layer so that each of the solder bumps is substantially aligned with a corresponding solder bump pad through a corresponding hole;
each solder bump penetrates into the solder paste inside the corresponding hole and electrically connects to the corresponding solder bump pad; and
the solder paste fills in a space between each of the solder bumps and the conductive inside walls of the corresponding holes thereby increasing contact area between the solder paste and the inside walls.
2. The package of claim 1 , wherein the solder bumps comprise stud bumps.
3. The package of claim 2 , wherein:
a diameter of each of the solder bumps is positioned in a direction substantially parallel to the substrate;
each corresponding hole has a diameter in a direction substantially parallel to the diameter of the solder bumps; and
the diameter of the holes is at least about twice the diameter of the solder bumps.
4. The package of claim 3 , wherein the circuit chip is bonded to the substrate by an adhesive.
5. The package of claim 1 , wherein the substrate further comprises:
a plurality of additional patterned conductive circuit layers; and
a plurality of additional insulating layers;
wherein:
the additional patterned conductive circuit layers and the additional insulating layers are layered in an alternating sequence;
at least a portion of each additional patterned conductive circuit layer is electrically coupled to a portion of an adjacent additional patterned conductive circuit layer via a conductor at least partially disposed through an intervening additional insulating layer; and
the first patterned conductive circuit layer is disposed on top of the plurality of additional patterned conductive circuit layers and the plurality of additional insulating layers.
6. The package of claim 1 , wherein the insulating layer comprises Bismaleimide-Taiazine (BT) or flame resistant FR-4 or FR-5.
7. The package of claim 1 , wherein the first patterned conductive circuit layer, the solder bump pads and the conductive inside walls comprises copper, gold, nickel, or a combination thereof.
8. A method, comprising:
forming a first patterned conductive circuit layer including a plurality of solder bump pads;
forming a first insulating layer covering the first patterned conductive circuit layer and having a plurality of holes to expose the solder bump pads, wherein each of the holes is positioned to accommodate at least a portion of a corresponding one of a plurality of solder bumps of a circuit chip, and wherein each of the holes includes a conductive inside wall;
filling the holes with conductive solder paste;
attaching the solder bumps on the circuit chip to the first patterned conductive circuit layer by having the solder bumps penetrate the solder paste inside the corresponding hole and electrically connect to the corresponding solder bump pad; and
melting the solder paste to cause the solder paste to collapse and fill in a space between each of the solder bumps and the conductive inside walls of the corresponding holes thereby increasing contact area between the solder paste and the inside walls.
9. The method of claim 8 , further comprising:
forming a plurality of additional patterned conductive circuit layers; and
forming a plurality of additional insulating layers;
wherein the additional patterned conductive circuit layers and the additional insulating layers are layered in an alternating sequence;
wherein at least a portion of each additional patterned conductive circuit layer is electrically coupled to a portion of an adjacent additional patterned conductive circuit layer via a conductor at least partially disposed through an intervening additional insulating layer; and
wherein the first patterned conductive circuit layer is disposed on top of the plurality of additional patterned conductive circuit layers and the plurality of additional insulating layers.
10. The method of claim 8 , wherein each of the holes has a diameter in a direction substantially parallel to the diameter of the solder bumps, and wherein the diameter of the holes is at least about twice the diameter of the solder bumps.
11. The method of claim 8 , farther comprising forming an adhesive layer on the first insulating layer, wherein the adhesive layer is patterned in accordance with the holes in the first insulating layer to expose the solder bump pads.