IP Library Granted Patent US 7,696,101
Granted Patent B2
US 7,696,101 · App. 11/263,885 · Granted Apr 13, 2010

Process for increasing feature density during the manufacture of a semiconductor device

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,696,101
App. No.
11/263,885
Granted
Apr 13, 2010
Kind
B2
Abstract

A method used during the manufacture of a semiconductor device comprises the formation of a first patterned layer having individual features of a first density. Through the formation and etching of various layers, for example conformal layers and a spun-on layer, a second patterned layer results which comprises individual features of a second density, which is about three times the first density. An in-process semiconductor apparatus formed using the method, and a system comprising the semiconductor apparatus formed according to the method, is also described.

Claims (60)

1. A method used to form a semiconductor device, comprising:

forming a patterned-first-support layer comprising a plurality of features over a layer to be etched, wherein each of the patterned-first-support layer features comprises first and second vertically oriented sidewalls;

after forming the patterned-first-support layer, forming a patterned-first-top-masking layer comprising a plurality of spacers, with each of the patterned-first-top-masking spacers being formed on a respective one of the vertically oriented sidewalls of a respective one of the patterned-first-support layer features;

prior to removing the patterned-first-support layer, forming a patterned-second-support layer comprising features, wherein each of the patterned-second-support layer features contacts a respective one of the patterned-first-top-masking layer spacers, and wherein each of a plurality of the patterned-second-support layer features is separated from an adjacent one of the patterned-second-support layer features by a gap;

prior to removing the patterned-first-support layer and the patterned-second-support layer, forming a patterned-second-top-masking layer which fills the gaps and comprises a plurality of spacers, wherein each of the plurality of patterned-second-top-masking layer spacers is separated from an adjacent one of the patterned-first-top-masking layer spacers by a respective one of the plurality of patterned-second-support layer features;

removing the patterned-first-support layer and the patterned-second-support layer; and

subsequent to removing the patterned-first-support layer and the patterned-second-support layer, etching the layer to be etched using patterned-first-top-masking layer and the patterned-second-top-masking layer as a mask.

2. The method of claim 1 further comprising:

forming an etch stop layer over the layer to be etched;

forming the patterned-first-top-masking layer and the patterned-second-top-masking layer on the etch stop layer;

patterning the etch stop layer using the patterned-first-top-masking layer and the patterned-second-top-masking layer as a pattern; and

etching the layer to be etched using the etch stop layer as a mask.

3. The method of claim 1 further comprising:

forming a bottom masking layer over the layer to be etched;

forming an etch stop layer over the bottom masking layer;

forming the patterned-first-top-masking layer and the patterned-second-top-masking layer on the etch stop layer;

patterning the etch stop layer using the patterned-first-top-masking layer and the patterned-second-top-masking layer as a pattern;

patterning the bottom masking layer using the pattern of the etch stop layer as a pattern;

etching the layer to be etched using the bottom masking layer as a mask.

4. The method of claim 3 further comprising trim etching the patterned bottom masking layer.

5. The method of claim 1 wherein forming the patterned-second-support layer comprises using a gas modulated etch process to form the patterned-second-support layer.

6. The method of claim 1 further comprising:

forming the plurality of patterned-first-support layer features to a first width;

forming the plurality of patterned-first-top-masking spacers to a second width which is about the same as the first width; and

forming the plurality of patterned-second-support layer features to a third width which is about the same as the first width, wherein a distance which spans each of the gaps is about the same as the first width.

7. The method of claim 6 wherein the first width, the second width, the third width, and the distance which spans each of the gaps is each about 33 nanometers.

8. A method used to form a semiconductor device, comprising:

forming a plurality of first-support features over a material to be etched, wherein each first-support feature comprises first and second vertically oriented sidewalls;

after forming the plurality of first-support features, forming a plurality of first-mask features, wherein a respective one of the first-mask features is formed on each vertically oriented sidewall of each first-support feature;

prior to removing the plurality of first-support features, forming second-support features, wherein each second-support feature contacts a respective one of the first-mask features, and wherein a plurality of the second-support features are each separated from an adjacent second-support feature by a gap;

prior to removing the plurality of first-support features and the plurality of second-support features, forming a plurality of second-mask features in the gaps, wherein each of the plurality of second-mask spacers is separated from an adjacent one of the first-mask features by a respective one of the plurality of second-support features;

removing the plurality of first-support features and the plurality of second-support features; and

subsequent to removing the plurality of first-support features and the plurality of second-support features, etching the material to be etched using a pattern of the plurality of first-mask features and the plurality of second-mask features as a mask.

9. The method of claim 8 , wherein:

forming a plurality of first-support features comprises forming a patterned-first-support layer;

forming a plurality of first-mask features comprises forming a plurality of spacers, wherein forming the plurality of spacers comprises forming a patterned-first-top-masking layer;

forming second-support features comprises forming a patterned-second-support layer;

forming a plurality of second-mask features comprises forming a patterned-second-top-masking layer which fills the gaps; and

wherein etching the material to be etched comprises etching a layer to be etched using the pattern of the patterned-first-top-masking layer and the pattern of the patterned-second-top-masking layer as the mask.

10. The method of claim 8 , further comprising forming an etch stop over the material to be etched, wherein the plurality of first-mask features and the plurality of second-mask features are formed on the etch stop, and wherein etching the material to be etched comprises patterning the etch stop using the pattern of the plurality of first-mask features and the plurality of second-mask features, wherein etching the material to be etched comprises using the patterned etch stop as a mask.

11. The method of claim 8 , wherein:

the plurality of first-support features are formed to a first width;

the plurality of first-mask features are formed to a second width which is about the same as the first width;

the plurality of second-support features are formed to a third width which is about the same as the first width; and

the gaps are formed to a fourth width which is about the same as the first width.

12. The method of claim 8 , wherein forming the plurality of first-mask features comprises forming a conformal mask layer and anisotropically etching the conformal mask layer to form spacers.

13. The method of claim 8 , wherein forming the second-support features comprises forming a conformal support layer and anisotropically etching the conformal support layer.

14. The method of claim 8 , wherein forming the plurality of second-mask features comprises:

depositing a blanket mask layer into each of the gaps, over the plurality of first-support features, over the plurality of first-mask features, and over the plurality of second-support features; and

removing the blanket mask layer from over the plurality of first-support features, from over the plurality of first-mask features, and from over the plurality of second-support features.

15. The method of claim 8 , wherein the plurality of first-mask features and the plurality of second-mask features comprise top-mask features, and further comprising:

forming a mask material over the material to be etched;

etching the mask material using the pattern of the top-mask features to transfer the pattern into the mask material; and

trim etching the mask material,

wherein etching the material to be etched using a pattern of the plurality of first-mask features and the plurality of second-mask features comprises etching the material to be etched using the trimmed mask material as a pattern.

16. The method of claim 8 , wherein the material to be etched comprises a semiconductor material.

17. The method of claim 8 , wherein the material to be etched comprises an etch stop material.

18. The method of claim 17 , wherein the etch stop material comprises one of an amorphous silicon and a low silane oxide.

19. The method of claim 8 , wherein the material to be etched comprises a layer of silicon nitride.

20. The method of claim 8 , wherein the plurality of first-support features comprise carbon, the plurality of first-mask features comprise tetraethyl orthosilicate (TEOS), the plurality of second-support features comprise a polymer formed using a gas modulated etch (GMODE) process, and the plurality of second-mask features comprise a silicon-containing polymer.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2005
From: LI, MINGTAO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 017179/0166 →
Continuity (1)
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