Granted Patent B2

US 7,701,765 · App. 11/646,658 · Granted Apr 20, 2010

Assignee: Micron Technology, Inc.

Abstract

Claims (112)

1. A method for programming an array of non-volatile multilevel memory cells, each cell having a number of lower pages and an upper page, the method comprising:

programming a first lower page of selected cells of a first word line;

programming a second lower page of the selected cells of the first word line;

programming a third lower page of the selected cells of the first word line;

programming an upper page of the selected cells of the first word line; wherein performing the first, the second, and the third lower page programming and the upper page programming for the selected cells of the first word line includes alternating between performing the first, the second, and the third lower page programming and the upper page programming for cells associated with an even and an odd bit line;

subsequently programming an upper page of selected cells of a second word line, the second word line adjacent the first word line; and

reprogramming the upper page of the selected cells of the first word line after the upper page programming of the selected cells of the second word line has finished;

wherein the method includes reprogramming the upper page of cells associated with even bit lines after the upper page programming of cells associated with odd bit lines has finished.

2. A method for programming an array of non-volatile multilevel memory cells, each cell having a number of lower pages and an upper page, the method comprising:

alternating between programming a first, a second, and a third lower page and an upper page for cells associated with an even and an odd bit line between a number of word lines; and

reprogramming the upper pages of cells of the even and the odd bit lines after a number of lower pages on different word lines have been programmed, including reprogramming the upper pages of selected cells of a first word line after programming of the upper pages of selected cells of a second word line has finished; and

wherein the method includes performing a reprogramming operation to reprogram the upper pages of cells associated with even bit lines after the upper page programming operation to program the upper page of cells associated with odd bit lines has finished.

3. The method of claim 2 , wherein the method includes:

beginning with a first word line adjacent to a source line of a NAND array of Flash non-volatile multilevel memory cells, alternating between programming the first, the second, and the third lower page and the upper page for cells associated with the even and the odd bit line between a number of next adjacent word lines;

reprogramming the upper pages of cells of the even and the odd bit lines after the third lower page of the even and the odd bit line associated with a third word line from the source line has been programmed.

4. The method of claim 3 , wherein the method includes reprogramming the upper pages of cells of the even and the odd bit lines after the upper page of the even and the odd bit line associated with a second word line from the source line has been programmed.

5. A method for programming a NAND array of non-volatile multilevel memory cells, each cell having a number of lower pages and an upper page, the method comprising:

beginning with a first word line adjacent to a source line of the NAND array, alternating between programming a first, a second, and a third lower page and an upper page for cells associated with an even and an odd bit line between a number of next adjacent word lines; and

reprogramming the upper pages of cells of the even and the odd bit lines after a number of lower pages on different word lines have been programmed, including reprogramming the upper pages of selected cells of the first word line after programming of the upper pages of selected cells of a second word line has finished; and

wherein the method includes performing a reprogramming operation to reprogram the upper pages of cells associated with even bit lines after the upper page programming operation to program the upper page of cells associated with odd bit lines has finished.

6. The method of claim 5 , wherein the method includes:

programming first lower pages of the even and the odd bit lines associated with the first word line;

next, programming first lower pages of the even and the odd bit lines associated with the second word line;

next, programming second lower pages of the even and the odd bit lines associated with the first word line;

next, programming first lower pages of the even and the odd bit lines associated with a third word line;

next, programming second lower pages of the even and the odd bit lines associated with the second word line; and

next, programming third lower pages of the even and the odd bit lines associated with the first word line.

7. The method of claim 6 , wherein the method includes;

programming first lower pages of the even and the odd bit lines associated a fourth word line;

programming second lower pages of the even and the odd bit lines associated with the third word line;

programming third lower pages of the even and the odd bit lines associated with the second word line;

programming upper pages of the even and the odd bit lines associated with the first word line; and

programming first lower pages of the even and the odd bit lines associated with the fifth word line.

8. The method of claim 7 , wherein the method includes:

programming second lower pages of the even and the odd bit lines associated with the fourth word line;

programming third lower pages of the even and the odd bit lines associated with the third word line;

programming upper pages of the even and the odd bit lines associated with the second word line; and

reprogramming upper pages of the even and the odd bit lines associated with the first word line.

9. A method for programming four bit non-volatile multilevel memory cells in a NAND array, each cell having a number of lower pages and an upper page, the method comprising:

beginning with a first word line adjacent to a source line of the NAND array, alternating between programming a first, a second, and a third lower page and an upper page for cells associated with an even and an odd bit line between a number of next adjacent word lines;

reprogramming the upper pages of cells of the even and the odd bit lines after a number of lower pages on different word lines have been programmed, including reprogramming the upper pages of selected cells of the first word line after programming of the upper pages of selected cells of a second word line has finished; and

wherein the method includes performing a reprogramming operation to reprogram the upper pages of cells associated with even bit lines after the upper page programming operation to program the upper page of cells associated with odd bit lines has finished.

10. The method of claim 9 , wherein the method includes:

programming a first lower page of the even bit line and a first lower page of the odd bit line associated with the first word line;

next, programming a first lower page of the even bit line and a first lower page of the odd bit line associated with the second word line;

next, programming a second lower page of the even bit line and a second lower page of the odd bit line associated with the first word line;

next, programming a first lower page of the even bit line and a first lower page of the odd bit line associated with a third word line;

next, programming a second tower page of the even bit line and a second lower page of the odd bit line associated with the second word line; and

next, programming a third lower page of the even bit line and a third lower page of the odd bit line associated with the first word tine.

11. The method of claim 10 , wherein the method includes:

programming a first lower page of the even bit line and a first tower page of the odd bit line associated a fourth word line;

programming a second lower page of the even bit line and a second lower page of the odd bit line associate with the third word line;

programming a third lower page of the even bit line and a third lower page of the odd bit tine associated with the second word line;

programming an upper page of the even bit line and an upper page of the odd bit line associated with the first word line; and

programming a first lower page of the even bit line and a first tower page of the odd bit line associated with a fifth word tine.

12. The method of claim 11 , wherein the method includes:

programming a second lower page of the even bit line and a second lower page of the odd bit line associated with the fourth word line;

programming a third lower page of the even bit line and a third tower page of the odd bit line associated with the third word line;

programming an upper page of the even bit line and an upper page of the odd bit line associated with the second word line; and

reprogramming the upper page of the even bit line and the upper page of the odd bit line associated with the first word line.

13. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and

control circuitry coupled to the array of non-volatile memory cells and configured to execute a method for programming data that includes:

alternately programming a first lower page in association with an even and an odd bit line between a number of word lines;

alternately programming a second lower page in association with the even and the odd bit line between the number of word lines;

alternately programming a third lower page in association with the even and the odd bit line between the number of word lines;

alternately programming an upper page in association with the even and the odd bit line between the number of word lines; and

alternately reprogramming the upper page of a cell in association with the even and the odd bit line between the number of word lines;

wherein the method includes:

performing a first, a second, and a third lower page programming operation and an upper page programming operation on selected cells of a first word line;

subsequently performing an upper page programming operation on selected cells of a second word line, the second word line adjacent the first word line; and

performing a reprogramming operation to reprogram the upper pages of the selected cells of the first word line after the upper page programming operation performed on the selected cells of the second word line has finished; and

wherein the method includes performing a reprogramming operation to reprogram the upper page of cells associated with the even bit line after the upper page programming operation to program the upper page of cells associated with the odd bit line has finished.

14. The device of claim 13 , wherein, each cell having a number of lower pages and an upper page, the method includes:

alternating between programming the first, the second, and the third lower page and the upper page for cells associated with the even and the odd bit line between the number of word lines; and

reprogramming the upper pages of cells of the even and the odd bit lines after a number of lower pages on different word lines have been programmed.

15. The device of claim 14 , wherein the method includes:

beginning with a first word line adjacent to a source line of a NAND array of Flash non-volatile multilevel memory cells, alternating between programming the first, the second, and the third lower page and the upper page for cells associated with the even and the odd bit line between a number of next adjacent word lines;

reprogramming the upper pages of cells of the even and the odd bit lines after the third lower page of the even and the odd bit line associated with a third word line from the source line has been programmed.

16. A non-volatile memory device, comprising:

an NAND array of multilevel non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines, each cell having a number of lower pages and an upper page; and

control circuitry coupled to the array of non-volatile memory cells and configured to execute a method for programming data that includes:

beginning with a first word line adjacent to a source line of the NAND array, alternating between programming a first, a second, and a third lower page and an upper page for cells associated with an even and an odd bit line between a number of next adjacent word lines;

reprogramming the upper pages of cells of the even and the odd bit lines after a number of lower pages on different word lines have been programmed, including reprogramming the upper pages of selected cells of the first word line after programming of the upper pages of selected cells of a second word line has finished; and

wherein the method includes performing a reprogramming operation to reprogram the upper pages of cells associated with even bit lines after the upper page programming operation to program the upper page of cells associated with odd bit lines has finished.

17. The device of claim 16 , wherein the method includes:

programming first lower pages of the even and the odd bit lines associated with the first word line;

next, programming first lower pages of the even and the odd bit lines associated with the second word line;

next, programming second lower pages of the even and the odd bit lines associated with the first word line;

next, programming first lower pages of the even and the odd bit lines associated with a third word line;

next, programming second lower pages of the even and the odd bit lines associated with the second word line; and

next, programming third lower pages of the even and the odd bit lines associated with the first word line.

18. The device of claim 17 , wherein the method includes:

programming first lower pages of the even and the odd bit lines associated a fourth word line;

programming second lower pages of the even and the odd bit lines associated with the third word line;

programming third lower pages of the even and the odd bit lines associated with the second word line;

programming upper pages of the even and the odd bit lines associated with the first word line; and

programming first lower pages of the even and the odd bit lines associated with a fifth word line.

19. The device of claim 18 , wherein the method includes:

programming second lower pages of the even and the odd bit lines associated with the fourth word line;

programming Third lower pages of the even and the odd bit lines associated with the third word line;

programming upper pages of the even and the odd bit lines associated with the second word line; and

reprogramming upper page of the even and the odd bit lines associated with the first word line.

20. A method for programming an array of non-volatile multilevel memory cells, each cell having an associated number of lower pages and an upper page, the method comprising:

performing a first, a second, and a third lower page programming operation and an upper page programming operation on selected cells of a first word line;

subsequently performing an upper page programming operation on selected cells of a second word line, the second word line adjacent the first word line; and

performing a reprogramming operation to reprogram the upper pages of the selected cells of the first word line after the upper page programming operation performed on the selected cells of the second word line has finished;

wherein performing the first, the second, and the third lower page programming and the upper page programming for selected cells of the first word line includes alternating between performing the first, the second, and the third lower page programming and the upper page programming for cells associated with an even and an odd bit line; and

wherein the method includes performing a reprogramming operation to reprogram the upper page of cells associated with the even bit lines after the upper page programming operation to program the upper page of cells associated with the odd bit lines has finished.

21. The method of claim 20 , wherein the method includes:

beginning with the first word line adjacent to a source line of The array, alternating between programming a first, a second, and a third lower page and an upper page for cells associated with an even and an odd bit line between a number of next adjacent word lines; and

reprogramming the upper pages of cells of the even and the odd bit lines between the number of next adjacent word lines according to a sequence such that the upper pages of memory cells are programmed after the upper page of each adjacent memory cell has been programmed.

Assignments (8)

Continuity (1)