IP Library Granted Patent US 7,745,868
Granted Patent B2
US 7,745,868 · App. 11/984,470 · Granted Jun 29, 2010

Semiconductor device and method of forming the same

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Quick Facts
Patent No.
US 7,745,868
App. No.
11/984,470
Granted
Jun 29, 2010
Kind
B2
Abstract

A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

Claims (28)

1. A semiconductor device comprising: a semiconductor substrate;

a MOS transistor having source and drain regions that are provided in the semiconductor substrate;

a first inter-layer insulator over the MOS transistor, the first inter-layer insulator having first contact holes that reach the source and drain regions;

cell contact plugs in the first contact holes, the cell contact plugs contact with the source and drain regions;

a second inter-layer insulator over the first inter-layer insulator and the cell contact plugs, the second inter-layer insulator having second contact holes that reach the cell contact plugs;

contact plugs each having first and second portions, the first portion being in the second contact hole, the second portion extending over the second inter-layer insulator;

metal barrier layers that cover the upper surfaces of the second portions of the contact plugs; and

capacitors each having a bottom electrode layer, a capacitive insulating layer and a top electrode layer, the bottom electrode layers each having a contact portion that contacts with the metal barrier layer.

2. The semiconductor device according to claim 1 , wherein the contact plugs are made of polysilicon.

3. The semiconductor device according to claim 1 , wherein the second portion of the contact plug is larger in the area in plan view than the contact portion of the bottom electrode layer.

4. The semiconductor device according to claim 1 , wherein the metal barrier layer has a single layered structure that includes one of a tungsten nitride layer and a titanium nitride layer.

5. The semiconductor device according to claim 1 , wherein the metal barrier layer comprises one of:

a first multilayered structure of a titanium nitride layer and a titanium silicide layer;

a second multilayered structure of a tungsten layer and a tungsten nitride layer;

a third multilayered structure of a tungsten nitride layer and a tungsten silicide layer;

a fourth multilayered structure of a tungsten layer, a tungsten nitride layer and a tungsten silicide layer; and

a fifth multilayered structure of a tungsten layer, a titanium nitride layer and a titanium silicide layer.

6. The semiconductor device according to claim 1 , wherein the metal barrier layer has a single layered structure that includes one of a titanium silicide layer, a cobalt silicide layer, and a tungsten silicide layer.

7. A semiconductor device comprising:

a first insulator having a first contact hole;

a first contact plug of polysilicon, the first contact plug having first and second portions, the first portion being in the first contact hole, the second portion extending over the first insulator, the first portion having a first dimension defined in a direction parallel to a surface of the first insulator, the second portion having a second dimension defined in the direction parallel to the surface of the first insulator, the second dimension being greater than the first dimension;

a metal barrier layer that contacts with at least an upper surface of the second portion of the first contact plug, the metal barrier layer having a metal-polysilicon interface with the first contact plug of polysilicon, the metal-polysilicon interface having a first area; and

a first metal electrode layer having a contact portion that contacts with a part of the metal barrier layer, the first metal electrode layer being separated by the metal barrier layer from the first contact plug of polysilicon, the first metal electrode layer having a metal-metal interface with the metal barrier layer, the metal-metal interface having a second area that is smaller than the first area, the contact portion of the first metal electrode having a third dimension defined in the direction parallel to the surface of the first insulator, the third dimension of the contact portion of the first metal electrode layer being smaller than the first dimension.

8. The semiconductor device according to claim 7 , wherein the metal barrier layer contacts with the upper surface and side edge of the second portion of the first contact plug.

9. The semiconductor device according to claim 7 , further comprising:

a semiconductor substrate;

a diffusion region in the semiconductor substrate; and

a second contact plug of polysilicon, the second contact plug having third and fourth portions, the third portion contacting with the diffusion region, the fourth portion contacting with the first portion of the first contact plug, the third portion having a third dimension defined in the direction parallel to the surface of the first insulator, the fourth portion having a fourth dimension defined in the direction parallel to the surface of the first insulator, the fourth dimension being greater than the third dimension and the first dimension.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →