Digital filters for semiconductor devices
A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the divider is configured to divide a count from the counter by a divisor.
1. An electronic device, comprising:
an internal data storage location; and
a digital filter coupled to the internal data storage location, wherein the digital filter comprises a counter and a divider, wherein the divider is configured to divide a count from the counter by a divisor, wherein the digital filter is coupled to the internal data storage location by an analog-to-digital converter.
2. The electronic device of claim 1 , wherein the internal data storage location comprises a data source selected from a floating-gate transistor, a phase-change memory element, a magneto-resistive memory element, or a photo-diode.
3. The electronic device of claim 1 , wherein the internal data storage location and digital filer are disposed on an integrated semiconductor device.
4. The electronic device of claim 1 , wherein the counter comprises a plurality of D flip-flops connected in series.
5. The electronic device of claim 1 , wherein the analog-to-digital converter comprises:
a comparator having first and second inputs and an output, wherein the output of the comparator is coupled to the digital filter, wherein the first input is coupled to an electrical conductor, and wherein the second input is coupled to a reference voltage source;
a capacitor having one plate coupled to the electrical conductor; and
a switch coupled to the electrical conductor in series with the internal data storage location, wherein the switch comprises a gate coupled to the output of the comparator.
6. The electronic device of claim 1 , wherein the divider is configured to transmit a first number of the most significant bits output from the counter and not transmit a second number of the least significant bits output from the counter.
7. An electronic device, comprising:
a plurality of internal data storage locations coupled to an electrical conductor in series;
an analog-to digital converter that is configured to output a pulse-density modulated bit-stream that has an average value that is generally proportional to the current through the electrical conductor; and
a digital filter comprising:
a counter with an output and an input, wherein the input is coupled to the plurality of internal data storage locations via the electrical conductor; and
a divider with an input and an output, wherein the input is coupled to the output of the counter.
8. The electronic device of claim 7 , wherein each of the internal data storage locations comprises a photo-diode.
9. The electronic device of claim 7 , wherein the divider is integrated with the counter and the counter is configured to increment a count by one when the bit-stream has a predetermined logic value at a predetermined time in a clock cycle.
10. The electronic device of claim 9 , wherein the digital filter is configured to output two or more of the most significant bits of a count formed by the counter and not output one or more less significant bits of the count.
11. The electronic device of claim 7 , wherein the counter is coupled to memory storing a preset value that is generally equal to an average rounding error of the divider.
12. A method of filtering a signal from an internal data storage location, the method comprising:
receiving a pulse-density modulated bit-stream;
integrating the pulse-density modulated bit-stream to calculate a sum; and
dividing the sum by a divisor to calculate an average value representative of a data value stored in an internal data storage location.
13. The method of claim 12 , comprising selecting the internal data storage location from among a plurality of internal data storage locations on an electrical conductor.
14. The method of claim 12 , comprising converting an analog signal by comparing a voltage of an electrical conductor to a reference voltage, wherein the electrical conductor is coupled to the internal data storage location.
15. The method of claim 12 , wherein the divisor is an integer exponent of a base numbering system used to represent the sum when dividing the sum.
16. The method of claim 12 , wherein dividing comprises dropping one or more of the least significant digits of the sum.
17. The method of claim 12 , comprising adding one-half of the divisor to or subtracting one-half of the divisor from the sum before dividing the sum by the divisor.
18. The method of claim 12 , comprising adding one-half to or subtracting one-half from the average after dividing the sum by the divisor and rounding the dividend after added or subtracting.
19. A digital filter, comprising:
an internal data storage location of a semiconductor device;
a counter coupled to the internal data storage location;
a divider coupled to an output of the counter, wherein the divider is configured to calculate an average value of a signal transmitted from the internal data storage location; and
a delta-sigma modulator, wherein the counter is connected to the internal data storage location via the delta-sigma modulator.
20. The digital filter of claim 19 , wherein the internal data storage location comprises a floating gate transistor.
21. The digital filter of claim 19 , wherein the divider comprises a digit of the counter and does not comprise another digit of the counter.
22. The digital filter of claim 21 , wherein the digit of the counter comprised by the divider is more significant than the other digit of the counter that is not comprised by the divider.
23. A system, comprising:
a computer system comprising:
a processor; and
a memory device coupled to the processor, wherein the memory device comprises:
a delta-sigma modulator coupled to a flash memory cell;
a counter coupled to the delta-sigma modulator; and
a divider coupled to the counter, wherein the divider is configured to filter data being transmitted from the flash memory cell to the processor.
24. The system of claim 23 , wherein the counter comprises a plurality of series connected D flip-flops.
25. The system of claim 23 , wherein the divider comprises an output of the counter that is not connected to a data bus, wherein the output of the counter represents a least significant bit of the counter.
26. The system of claim 23 , wherein the computer system comprises a mother board coupled to the processor and the memory device, a video card coupled to the mother board, a hard drive coupled to the mother board, and a power supply coupled to the mother board.