IP Library › Granted Patent US 7,776,734
Granted Patent B2
US 7,776,734 · App. 11/441,841 · Granted Aug 17, 2010

Barrier layer for fine-pitch mask-based substrate bumping

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,776,734
App. No.
11/441,841
Granted
Aug 17, 2010
Kind
B2
Abstract

A structure that may be used in substrate solder bumping comprises a substrate ( 110 ), a solder resist layer ( 120 ) disposed over the substrate, a plurality of solder resist openings ( 121 ) in a surface ( 122 ) of the solder resist layer, a conformal barrier layer ( 130 ) having a first portion ( 131 ) over the surface of the solder resist layer and a second portion ( 132 ) in the solder resist openings, a mask layer ( 140 ) over the first portion of the conformal barrier layer, and a solder material ( 150 ) in the solder resist openings over the metal layer. The conformal barrier layer acts as a barrier against interaction between the solder resist layer and the mask layer during solder reflow.

Claims (31)

1. A method comprising:

providing a substrate having a solder resist layer disposed thereon, the solder resist layer having a surface and a plurality of solder resist openings within the surface;

forming a conformal barrier layer having a first portion over the surface of the solder resist layer and a second portion in the solder resist openings;

forming a mask layer over the first portion of the conformal barrier layer;

depositing a solder material in at least some of the solder resist openings;

reflowing the solder material to form solder bumps in the solder resist openings;

removing the mask layer; and

removing the first portion of the conformal barrier layer, wherein said method further comprises treating the solder resist layer so as to improve its ability to adhere to the conformal barrier layer.

2. The method of claim 1 wherein:

treating the solder resist layer comprises roughening a surface of the solder resist layer.

3. The method of claim 1 further comprising:

treating the conformal barrier layer so as to improve its ability to adhere to the mask layer.

4. The method of claim 3 wherein:

treating the conformal barrier layer comprises roughening a surface of the conformal barrier layer.

5. The method of claim 1 wherein:

forming the conformal barrier layer comprises electrolessly depositing the conformal barrier layer.

6. The method of claim 5 wherein:

forming the conformal barrier layer comprises electrolessly depositing a nickel layer; and

the method further comprises forming a metal layer in the solder resist openings over the second portion of the conformal barrier layer.

7. The method of claim 6 wherein:

forming the metal layer comprises forming a layer of gold.

8. The method of claim 5 wherein:

forming the conformal barrier layer comprises electrolessly depositing a metal selected from the group consisting of silver and tin.

9. The method of claim 1 wherein:

forming the mask layer comprises forming a dry film resist layer.

10. The method of claim 1 wherein:

removing the mask layer comprises stripping the mask layer.

11. The method of claim 1 wherein:

removing the first portion of the conformal barrier layer comprises etching the first portion of the conformal barrier layer.

12. The method of claim 11 wherein:

etching the first portion of the conformal barrier layer comprises using an etchant selected from the group consisting of tin chloride and sulfuric acid to etch the first portion of the conformal barrier layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076065/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2009
From: NALLA, RAVI K.; TSAU, CHRISTINE H.; HLAD, MARK S.
To: INTEL CORPORATION
Reel/Frame 022941/0840 →
Continuity (1)
Related Publication 20070275550A1 · Nov 29, 2007