Semiconductor device and fabrication method thereof

1. A semiconductor device, comprising:

a silicon substrate including a channel region therein;

a gate electrode formed on said silicon substrate via a gate insulation film in correspondence to said channel, said gate electrode carrying a pair of sidewall insulation films on respective, mutually opposing sidewall surfaces thereof;

source and drain extension regions of a p-type diffusion region formed in said silicon substrate at both lateral sides of said gate electrode so as to oppose with each other across said channel region;

source and drain regions of a p-type diffusion region formed in said silicon substrate at respective outer sides of said sidewall insulation films respectively in continuation to said source and drain extension regions; and

a pair of SiGe mixed crystal regions formed in said silicon substrate at respective outer sides of said sidewall insulation films in epitaxial relationship to said silicon substrate, said SiGe mixed crystal regions being formed so as to be included by said source and drain regions respectively;

each of said SiGe mixed crystal regions being grown to a height beyond a gate insulation film interface formed between said gate insulation film and said silicon substrate,

said SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other,

wherein, in each of said SiGe mixed crystal regions, said sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of said silicon substrate,

wherein said semiconductor device further comprises a p-type Si layer on each of said SiGe mixed crystal regions, a silicide layer being formed in said p-type Si layer.

2. The semiconductor device as claimed in claim 1 , wherein said principal surface of said silicon substrate forms a (001) surface, said gate electrode extending on said silicon substrate generally in any of a <110> direction and a <100> direction.

3. The semiconductor device as claimed in claim 1 , wherein each of SiGe mixed crystal regions contains Ge with a concentration level exceeding 20% in terms of atomic percent.

4. The semiconductor device as claimed in claim 3 , wherein said concentration level does not exceed 40% in terms of atomic percent.

5. The semiconductor device as claimed in claim 1 , wherein each of said pair of SiGe mixed crystal regions has a thickness of 20-70 nm for a part thereof located underneath said gate insulation film interface and a thickness of 0-30 nm for a part thereof located on or above said gate insulation film interface.

6. The semiconductor device as claimed in claim 1 , wherein, in each of said pair of SiGe mixed crystal regions, each of said plurality of facets has a planarized surface.

7. The semiconductor device as claimed in claim 1 , wherein, in each of said pair of SiGe mixed crystal regions, each of said plurality of facets is defined by a crystal surface.

8. The semiconductor device as claimed in claim 1 , wherein, in each of said pair of SiGe mixed crystal regions, said plurality of facets includes an uppermost facet formed such that a distance between said mutually facing sidewall surfaces of said SiGe mixed crystal regions increases in an upward direction of said silicon substrate, said uppermost facet defining an uppermost part of said SiGe mixed crystal region located above said gate insulation film interface.

9. The semiconductor device as claimed in claim 1 , wherein said silicide layer has a bottom surface located above said gate insulation film interface.

10. The semiconductor device as claimed in claim 1 , wherein said p-type Si layer is substantially free from Ge.