Method for producing deep trench structures

1. A method for producing deep trench structures in an STI structure of a semiconductor substrate, the method comprising:

providing at least one STI recess into a respective at least one portion of said semiconductor substrate;

providing materials to form an active region on a second portion of said semiconductor substrate;

introducing a first filler material to provide full-area filling of each of said at least one STI recess and to cover said active region to form a semiconductor structure;

subjecting a first surface of said semiconductor structure to a CMP process to level said first filler material and produce the STI structure, wherein the STI structure is a level planar surface across the entirety of the full-area filling and the active region; and

etching at least one deep trench, using the leveled STI structure as a hard mask, in an area of the STI structure to create the deep trench structures.

2. A method for producing deep trench structures in an STI structure of a semiconductor substrate, the method comprising:

a) preparing a semiconductor substrate having at least one STI recess and at least one active region for a semiconductor component or a part thereof;

b) full-area application of a first filler material on the semiconductor substrate, including the active region and in the region of the at least one STI recess, to produce a first filler layer and form a semiconductor structure;

c) CMP polishing of a first surface of said semiconductor structure to level the first filler layer that was applied in a full-area manner and to provide a level planar surface across the entirety of the filler layer and the active region of said semiconductor structure;

d) structuring of a second surface produced by CMP polishing on the first filler layer to form a hard mask;

e) etching of at least one deep trench using deep trench technology and the hard mask:

f) full-area deposition of a second filler layer to fill the deep trenches;

g) back-etching of excess material of the second filler layer from a third surface of the semiconductor structure and/or the deep trenches.

3. The method according to claim 2 , wherein, after the process step (g), a third filler layer is applied in a full-area manner to the unfilled regions of the deep trenches and to the semiconductor structure.

4. The method according to claim 2 , wherein, prior to the full-area application of the first filler material to the semiconductor substrate, a layer stack serving to define the active region and/or serving as an additional hard mask for etching at least one STI recess is applied to a surface of the semiconductor substrate.

5. The method according to claim 2 , wherein the deposited first filler layer in the area of the STI recesses has a first layer thickness that is at least large enough that, in vertical projection, a first surface of the first filler layer is provided at least at a height of the layer stack in an area of the active region.

6. The method according to claim 2 , wherein an additional thin dielectric layer is arranged between the first filler layer and the semiconductor substrate of the semiconductor structure in a region of the STI structure.

7. The method according to claim 2 , wherein, to create the hard mask, a lacquer layer is first applied to the second surface and is structured, and wherein, using the structured lacquer layer, the STI filler layer is etched completely through in a region of openings in the structured lacquer layer to form additional trenches in the hard mask.

8. The method according to claim 2 , wherein an anisotropic etching method is used to etch the deep trenches and/or to create the hard mask and/or to etch the STI recesses.

9. The method according to claim 2 , wherein the first filler layer and/or the second filler layer and/or the third filler layer and/or the layer stack has a dielectric material.

10. The method according to claim 2 , wherein the first filler layer and/or the second filler layer and/or the third filler layer and/or the layer stack has an electrically conductive material.

11. The method according to claim 2 , wherein the first filler layer and/or the second filler layer and/or the third filler layer and/or the layer stack has doped polysilicon.

12. The method according to claim 5 , wherein the CMP process is controlled by the first layer thickness.

13. The method according to claim 9 , wherein silicon dioxide and/or TEOS oxide and/or silicon nitride is provided as the dielectric material.