Trench formation in a semiconductor material
A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.
1. A method for forming a semiconductor device on a semiconductor layer, comprising:
forming a gate dielectric layer over the semiconductor layer;
forming a layer of gate material over the gate dielectric layer;
patterning the layer of gate material to form a gate structure;
implanting into the semiconductor layer using the gate structure as a mask;
etching through the gate structure to form a first patterned gate structure and through the semiconductor layer to form a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the first patterned gate structure, wherein the step of etching through the gate structure is further characterized by forming a second patterned gate structure wherein the first and second patterned gate structures are separated only by a width of the trench; and
filling the trench with insulating material.
2. The method of claim 1 further comprising:
forming a sidewall spacer on a sidewall of the gate structure; and
implanting into the first portion and the second portion using the gate structure and the sidewall spacer as a mask.
3. The method of claim 1 further comprising electrically connecting a conductive line to the first patterned gate structure.
4. The method of claim 1 further comprising:
after the step of filling the trench, forming in the semiconductor layer a stressor layer over the first portion, the first patterned gate structure, and the second portion, wherein the stressor layer has a height over the first and second portions that is greater than a height of the first patterned gate structure.
5. The method of claim 1 , wherein the step of etching is further characterized by the first patterned gate structure having ends coterminous with the trench in the semiconductor layer, the first portion is on a first side of the first patterned gate structure and the second portion is on a second side of the first patterned gate structure.
6. The method of claim 1 , wherein the step of filling the trench comprises:
forming trench sidewall spacers on sidewalls of the trench; and
depositing an insulating material in the trench after the step of forming the trench sidewall spacers.
7. The method of claim 3 , wherein the step of electrically connecting comprises:
depositing an insulating layer over a substrate;
forming a trench in the insulating layer over at least a portion of the gate; and
filling the trench in the insulating layer with conductive material.
8. The method of claim 3 , wherein the step of electrically connecting comprises:
depositing a metal layer over the first patterned gate structure; and
patterning the metal layer to leave a portion of the metal layer over the first patterned gate structure.
9. The method of claim 4 , wherein the step of forming the stressor is further characterized by the stressor comprising nitride.
10. A method for forming a semiconductor device on a semiconductor layer, comprising:
forming a gate structure over the semiconductor layer;
performing an implant using the gate structure as a mask;
defining an active region in the semiconductor layer, after the step of implanting, by etching through the gate structure and the semiconductor layer to form a trench in the semiconductor layer, wherein the etching results in a first patterned gate structure and a second patterned gate structure in the active region, and wherein first and second patterned gate structures are separated only by a width of the trench; and
depositing isolation material in the trench.
11. The method of claim 10 , wherein the step of defining is further characterized by each of the first patterned gate structure and the second patterned gate structure having two ends in which each end is coterminous with a boundary of the active region defined by the trench.
12. The method of claim 11 , wherein the step of forming the gate structure further comprises:
forming a high k dielectric as a gate dielectric on the semiconductor layer prior to forming the gate structure.
13. The method of claim 11 further comprising:
after the step of filling the trench, forming a stressor over the active region adjacent to the first patterned gate structure and over the first patterned gate structure; and
electrically connecting a conductive line to the first patterned gate structure.
14. The method of claim 13 , wherein the step of forming the stressor is further characterized by the stressor having a height over active region adjacent to the first patterned gate structure that is above a height of the first patterned gate structure.
15. The method of claim 13 further comprising:
after the step of filling the trench, forming the stressor over the active region adjacent to the second patterned gate structure and over the second patterned gate structure; and
electrically connecting the conductive line to the second patterned gate structure.
16. The method of claim 13 , wherein the step of forming the stressor is further characterized by the stressor having a height over active region adjacent to the second patterned gate structure that is above a height of the second patterned gate structure.
17. A method for forming a semiconductor device on a semiconductor layer, comprising:
forming a gate dielectric layer over the semiconductor layer;
forming a layer of gate material over the gate dielectric layer;
patterning the layer of gate material to form a gate structure;
implanting into the semiconductor layer using the gate structure as a mask to form source/drain regions;
forming a silicide layer over the gate structure and the source/drain regions;
after forming the silicide layer, etching through the gate structure, the silicide layer, and the semiconductor layer to form a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer, wherein the etching results in a first patterned gate structure and a second patterned gate structure separated only by a width of the trench;
filling the trench with insulating material; and
electrically connecting a conductive line to the first patterned gate structure, wherein electrically connecting the conductive line comprises depositing a conductive layer over the first patterned gate structure and the second patterned gate structure and patterning the conductive layer to leave a portion of the conductive layer over the first patterned gate structure and the second patterned gate structure to interconnect the first patterned gate structure and the second patterned gate structure.
18. The method of claim 17 further comprising:
after forming the silicide layer over the gate structure and the source/drain regions, forming a nitride layer over the silicide layer.
19. The method of claim 18 further comprising:
prior to filling the trench with the insulating material, forming trench sidewall spacers in the trench.