Enhancement mode gallium nitride power devices
Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.
1. A Ga-face enhancement mode high electrode mobility transistor device, comprising:
a GaN buffer layer;
a p-type bottom cap on the GaN buffer layer;
a GaN channel layer on an opposite side of the bottom cap from the GaN buffer layer;
an Al x GaN layer on an opposite side of the GaN channel layer from the cap layer;
a p-type top cap on an opposite side of the Al x GaN layer from the channel layer;
a top gate adjacent to the top cap;
a source and a drain; and
an access region between either the source and the gate or the drain and the gate.
2. The device of claim 1 , wherein the top cap is formed of p-type Al z GaN.
3. The device of claim 1 , wherein the bottom cap is formed of p-type GaN.
4. The device of claim 1 , wherein the bottom cap is formed of Al y GaN, wherein y varies from one surface to an opposite surface of the bottom cap.
5. The device of claim 1 , wherein the Al x GaN layer has a thickness of less than 500 Angstroms.
6. The device of claim 1 , wherein the channel layer has a thickness of less than 300 Angstroms.
7. The device of claim 1 , further comprising a layer of Al y GaN laterally surrounding the top cap, where y>x.
8. The device of claim 1 , wherein the device has an internal barrier of at least 0.5 eV when no voltage is applied to the gate.
9. The device of claim 1 , wherein the GaN buffer layer has an aperture exposing the bottom cap.
10. The device of claim 9 , further comprising a bottom gate in the aperture and contacting the bottom cap.
11. The device of claim 1 , wherein the access region is doped.
12. The device of claim 11 , wherein the access region is doped with a donor species.
13. A method of making the device of claim 1 , comprising:
forming a structure including the GaN buffer, GaN channel layer and Al x GaN layer;
forming the p-type top cap on the Al x GaN layer;
forming the top gate adjacent to the p-type top cap;
applying a passivation layer over the p-type top cap and Al x GaN layer;
bonding a carrier wafer onto the passivation layer; and forming the aperture in the GaN buffer layer.
14. The method of claim 13 , further comprising forming a bottom gate in the aperture in the GaN buffer layer.