Through-silicon via formed with a post passivation interconnect structure
View Patent ↗An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV.
1. An integrated circuit structure, comprising:
a semiconductor substrate;
a through-silicon via (TSV) extending into the semiconductor substrate;
a pad formed over the semiconductor substrate and spaced apart from the TSV; and
an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad;
wherein the interconnect structure comprises
an upper portion which is formed on the pad and extends to electrically connect the TSV; and
a lower portion outside the TSV and adjacent and directly in contact with the pad.
2. An integrated circuit structure, comprising:
a semiconductor substrate;
a through-silicon via (TSV) extending into the semiconductor substrate;
a pad formed over the semiconductor substrate and spaced apart from the TSV; and
an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad;
wherein the interconnect structure comprises an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV; and
wherein the lower portion of the interconnect structure is a ring surrounding and directly in contact with the pad.
3. The integrated circuit structure of claim 1 , wherein the interconnect structure and the TSV are formed of the same conductive material.
4. The integrated circuit structure of claim 1 , wherein at least one of the TSV or the interconnect structure comprises copper.
5. The integrated circuit structure of claim 1 , wherein the pad comprises aluminum or an aluminum alloy.
6. The integrated circuit structure of claim 1 , further comprising
a passivation layer formed between the semiconductor substrate and the upper portion of the interconnect structure and surrounding the lower portion of the interconnect structure.
7. The integrated circuit structure of claim 6 , wherein the passivation layer extends into the semiconductor substrate to line the sidewall and bottom of the TSV.
8. The integrated circuit structure of claim 6 , wherein the passivation layer comprises two isolation layers.
9. The integrated circuit structure of claim 6 , wherein the passivation layer comprises silicon oxide, silicon nitride, or a combination thereof.
10. An integrated circuit structure, comprising:
a semiconductor substrate;
a low-k dielectric layer over the semiconductor substrate;
a metal line formed in the low-k dielectric layer;
a first passivation layer formed on the low-k dielectric layer and exposing a portion of the metal line;
a pad formed in the first passivation layer and on the exposed portion of the metal line;
a through-silicon via (TSV) passing through the first passivation layer and the low-k dielectric layer and extending into the semiconductor substrate, wherein the TSV is spaced apart from the pad; and
an interconnect structure formed over the first passivation layer and electrically connecting the TSV and the pad;
wherein the interconnect structure comprises
an upper portion which is formed directly on the pad and extends laterally into direct electrical connection with the TSV; and
a lower portion which extends from the upper portion toward the substrate, is located outside the TSV, and is in direct contact with the pad.
11. The integrated circuit structure of claim 10 , wherein the lower portion of the interconnect structure is a ring surrounding the pad.
12. The integrated circuit structure of claim 10 , wherein the interconnect structure and the TSV are formed of the same conductive material.
13. The integrated circuit structure of claim 10 , wherein at least one of the TSV or the interconnect structure comprises copper.
14. The integrated circuit structure of claim 10 , wherein the pad comprises at least one of aluminum, copper, an aluminum alloy, or a copper alloy.
15. The integrated circuit structure of claim 10 , further comprising
a second passivation layer formed between the first passivation layer and the upper portion of the interconnect structure and surrounding the lower portion of the interconnect structure.
16. The integrated circuit structure of claim 15 , wherein the second passivation layer extends into the semiconductor substrate to line the sidewall and bottom of the TSV.
17. The integrated circuit structure of claim 15 , wherein the second passivation layer comprises at least one of silicon oxide, silicon nitride, or a combination thereof.
18. The integrated circuit structure of claim 10 , wherein the first passivation layer comprises at least one of silicon oxide, silicon nitride, or a combination thereof.
19. The integrated circuit structure of claim 1 , wherein the lower portion of the interconnect structure is positioned between the TSV and the pad.
20. The integrated circuit structure of claim 1 , wherein the lower portion of the interconnect structure is co-elevational with the pad.