Asynchronous circuit logical verification method, logical verification apparatus, and computer readable storage medium
A verification method for verifying an asynchronous circuit includes producing a netlist based on circuit information at a register transfer level, extracting delay information and an asynchronous circuit section in which circuits operating with different clock signals are coupled to each other from the netlist, processing the delay information to extend a malfunction generating period in the asynchronous circuit section, and executing verification of the asynchronous circuit based on the delay information having been processed.
1. A logical verification method for verifying an asynchronous circuit using a processor, the method comprising:
producing a netlist based on circuit information at a register transfer level with the processor;
extracting delay information and an asynchronous circuit section in which circuits operating with different clock signals are coupled to each other from the netlist;
processing the delay information to extend a period that generates a malfunction in the asynchronous circuit section; and
executing verification of the asynchronous circuit based on the delay information having been processed.
2. The logical verification method according to claim 1 , further comprising:
processing the delay information;
changing a wiring delay value of wiring coupled to an input terminal of an information receiving-side circuit in the asynchronous circuit section; and
extending the malfunction generating period.
3. The logical verification method according to claim 1 , further comprising processing the delay information such that a delay time from an input to an output of each circuit cell in the netlist is set to 0.
4. The logical verification method according to claim 1 , further comprising:
processing the delay information; and
setting a wiring delay value of wiring coupled to an input terminal of the flip-flop to a minimum setting value when the circuit cell is a flip-flop.
5. The logical verification method according to claim 1 , further comprising:
processing the delay information;
subtracting a minimum setting value from a cycle of a clock signal input to the receiving-side circuit, on the falling side thereof, to obtain a value; and
setting the wiring delay value of the wiring, which is coupled to the input terminal of a receiving-side circuit, to the minimum setting value on the rising side of a signal transmitted through the wiring and to the value.
6. The logical verification method according to claim 1 , further comprising:
processing the delay information;
subtracting a minimum setting value from a cycle of a clock signal input to a receiving-side circuit, on the rising side of a signal transmitted through the wiring and to the minimum setting value on the falling side thereof, to obtain a value; and
setting the wiring delay value of the wiring, which is coupled to the input terminal of the receiving-side circuit, to the value.
7. The logical verification method according to claim 1 , further comprising:
processing the delay information; and
setting a wiring delay value of the wiring, which is coupled to the input terminal of the receiving-side circuit, to a minimum setting value on each of the rising side and the falling side of a signal transmitted through the wiring.
8. The logical verification method according to claim 1 , further comprising:
processing the delay information;
subtracting a minimum setting value from a cycle of a clock signal input to a receiving-side circuit, on each of the rising side and the falling side of a signal transmitted through the wiring to obtain a value; and
setting a wiring delay value of the wiring, which is coupled to an input terminal of the receiving-side circuit, to the value.
9. The logical verification method according to claim 1 , further comprising executing the verification when a clock signal is input and when a reversed clock signal obtained by reversing the clock signal is input.
10. The logical verification method according to claim 4 , wherein the input terminal is a data terminal or an enable terminal of the flip-flop.
11. A logical verification apparatus for verifying an asynchronous circuit, comprising:
a logical synthesis section producing a netlist based on circuit information at a register transfer level;
an extraction section extracting, from the netlist, delay information and an asynchronous circuit section in which circuits operating with different clock signals are coupled to each other;
a delay information processing section processing the delay information to extend a period that is generating a malfunction in the asynchronous circuit section; and
a simulation section executing verification of the asynchronous circuit based on the delay information having been processed.
12. A program stored on a non-transitory computer readable storage medium and causing a computer to execute a process for verifying an asynchronous circuit, the program comprising operation of the computer to function as:
a logical synthesis section producing a netlist based on circuit information at a register transfer level;
an extraction section extracting, from the netlist, delay information and an asynchronous circuit section in which circuits operating with different clock signals are coupled to each other;
a delay information processing section processing the delay information to extend a period that is generating a malfunction in the asynchronous circuit section; and
a simulation section executing verification of the asynchronous circuit based on the delay information having been processed.