Contact forming method and related semiconductor device
View Patent ↗Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
1. A semiconductor device comprising:
a gate structure including a dielectric cap;
a contact adjacent to the gate structure, the contact extending over a corner of the gate structure and over at least a portion of a top surface of the gate structure;
a first liner extending over the gate structure, including over the corner of the gate structure, and over a substrate below the gate structure;
a second liner over a portion of the first liner, the second liner extending only over the corner of the gate structure and along the sidewall of the gate structure and along an entire sidewall of the contact, wherein a bottom of the contact directly contacts a source/drain region within the substrate; and
a contact liner extending over the second liner and along the entire sidewall of the contact, wherein the second liner and the contact liner include different materials.
2. The semiconductor device of claim 1 , wherein the gate structure has a size in a 90 nm technology or beyond.
3. The semiconductor device of claim 1 , wherein at least one of the first liner and the second liner includes an intrinsic stress.
4. The semiconductor device of claim 1 , wherein the first liner has a thickness in the range of approximately 20 nm to approximately 2000 nm, and the second liner has a thickness in a range of approximately 5 nm to approximately 20 nm.
5. The semiconductor device of claim 1 , wherein the first liner includes silicon nitride.