Dielectric material separated-type, high breakdown voltage semiconductor circuit device, and production method thereof
A dielectrically isolated semiconductor device of high reliability is provided by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. The dielectrically isolated semiconductor device includes an SOI substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and an element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer, and which is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and a polycrystalline semiconductor layer formed between the second insulation films.
1. A dielectrically isolated semiconductor device comprising:
a semiconductor substrate;
a first insulation film formed on one side of the semiconductor substrate; and
a first doped semiconductor layer formed on the first insulation film; wherein:
the first doped semiconductor layer is deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device,
the first doped semiconductor layer includes an active device region in which an element is formed and an element isolating region which encloses the active device region,
the element isolating region is provided with a plurality of trenches coming into contact with the first insulation film and structured to form a two-dimensional closed loop, and
each of the trenches is filled with second doped layers, doped with n-type impurities and doped more heavily than the first doped semiconductor layer, and second insulation films each adjacent to one of the second doped layers,
wherein the element isolating layer has an n-multiple structure including the plurality of trenches, and further comprising polycrystalline semiconductor layers, the second insulation layers adjacent to each side of the polycrystalline semiconductor layer, and the second doped layers, respectively, adjacent to each side of the second insulation layers, said adjacent layers comprising n-multiple polycrystalline silicon layers, 2n-multiple second insulation layers and (n+1)-multiple second doped layers.
2. The dielectrically isolated semiconductor device according to claim 1 , wherein a third doped layer, more heavily doped than the first doped semiconductor layer, is formed between the first insulation film and the first doped semiconductor layer.
3. The dielectrically isolated semiconductor device according to claim 1 , wherein each of the first and second insulation films is comprised of a silicon oxide film formed by a thermal oxidation.
4. The dielectrically isolated semiconductor device according to claim 1 , wherein the second doped layers, and second insulation layers and polycrystalline semiconductor layers, are formed in a self-aligning manner with the trench coming into contact with the first insulation layer.
5. A predriver IC which includes the dielectrically isolated semiconductor device according to claim 1 .
6. A one-chip inverter which includes the dielectrically isolated semiconductor device according to claim 1 .
7. The dielectrically isolated semiconductor device according to claim 1 , wherein the second doped layers are doped with n + impurity.
8. The dielectrically isolated semiconductor device according to claim 1 ,
wherein the second insulation layers are comprised of an oxide.
9. The dielectrically isolated semiconductor device according to claim 7 ,
wherein the second insulation layers are comprised of an oxide.