Method of joining chips utilizing copper pillar

1. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip and a first tin-containing layer over said copper pillar, wherein said first tin-containing layer has a thickness less than a thickness of said copper pillar;

providing a second tin-containing layer on a substrate, wherein said second tin-containing layer has a thickness less than said thickness of said copper pillar; and

after said providing said copper pillar on said chip and said first tin-containing layer over said copper pillar and said providing said second tin-containing layer on said substrate, joining said chip with said substrate, wherein said joining said chip with said substrate comprises joining said first tin-containing layer with said second tin-containing layer, wherein said first tin-containing layer contacts said second tin-containing layer, wherein said chip remains joined with said substrate.

2. The method of claim 1 further comprising said providing said copper pillar over a pad in said chip, wherein said copper pillar has a width less than that of said pad.

3. The method of claim 1 , wherein said first tin-containing layer comprises silver.

4. The method of claim 1 , wherein said providing said second tin-containing layer comprises a screen-printing process.

5. The method of claim 1 , wherein said second tin-containing layer comprises silver.

6. The method of claim 1 , wherein said joining said first tin-containing layer with said second tin-containing layer comprises a reflow process.

7. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip and a tin-containing layer over said copper pillar, wherein said tin-containing layer has a thickness less than a thickness of said copper pillar;

providing a gold-containing layer on a substrate, wherein said gold-containing layer has a thickness less than said thickness of said copper pillar; and

after said providing said copper pillar on said chip and said tin-containing layer over said copper pillar and said providing said gold-containing layer on said substrate, joining said chip with said substrate, wherein said joining said chip with said substrate comprises joining said tin-containing layer with said gold-containing layer, wherein said tin-containing layer contacts said gold-containing layer, wherein said chip remains joined with said substrate.

8. The method of claim 7 further comprising said providing said copper pillar over a pad in said chip, wherein said copper pillar has a width less than that of said pad.

9. The method of claim 7 , wherein said tin-containing layer comprises silver.

10. The method of claim 7 , wherein said joining said tin-containing layer with said gold-containing layer comprises a reflow process.

11. A method for fabricating a chip package, comprising:

providing a metal bump on a chip, wherein said metal bump comprises a copper pillar over said chip;

providing a tin-containing layer on a substrate, wherein said tin-containing layer has a thickness greater than 15 micrometers and less than a thickness of said copper pillar; and

joining said chip with said substrate, wherein said joining said chip with said substrate comprises joining said metal bump with said tin-containing layer using a process comprising a reflow process, wherein said metal bump contacts said tin-containing layer, wherein said chip remains joined with said substrate.

12. The method of claim 11 , wherein said tin-containing layer comprises silver.

13. The method of claim 11 , wherein said tin-containing layer comprises silver and copper.

14. The method of claim 11 , wherein said tin-containing layer comprises lead.

15. A method for fabricating a chip package, comprising:

providing a copper pillar on a chip and a first gold-containing layer over said copper pillar, wherein said first gold-containing layer has a thickness less than a thickness of said copper pillar;

providing a second gold-containing layer on a substrate, wherein said second gold-containing layer has a thickness less than said thickness of said copper pillar; and

after said providing said copper pillar on said chip and said first gold-containing layer over said copper pillar and said providing said second gold-containing layer on said substrate, joining said chip with said substrate, wherein said joining said chip with said substrate comprises joining said first gold-containing layer with said second gold-containing layer, wherein said first gold-containing layer contacts said second gold-containing layer, wherein said chip remains joined with said substrate.

16. The method of claim 15 further comprising said providing said copper pillar over a pad in said chip, wherein said copper pillar has a width less than that of said pad.

17. A method for fabricating a multi-chip structure, comprising:

providing a copper layer on a first chip and a first tin-containing layer over said copper layer;

providing a second tin-containing layer on a second chip; and

after said providing said copper layer on said first chip and said first tin-containing layer over said copper layer and said providing said second tin-containing layer on said second chip, joining said first chip with said second chip, wherein said joining said first chip with said second chip comprises joining said first tin-containing layer with said second tin-containing layer, wherein said first tin-containing layer contacts said second tin-containing layer, wherein said first chip remains joined with said second chip.

18. The method of claim 17 , wherein said first tin-containing layer comprises silver.

19. The method of claim 17 , wherein said first tin-containing layer comprises indium.

20. The method of claim 17 , wherein said second tin-containing layer comprises silver.