Granted Patent B2

US 8,024,694 · App. 12/365,084 · Granted Sep 20, 2011

Abstract

Claims (22)

1. A method of standardized data creation and analysis of semiconductor technology node characteristics, comprising: using a computer for:

designing at least one representative benchmark circuit;

establishing standard sensitization and measurement rules for delay and power for said at least one representative benchmark circuit and across corners in said technology nodes;

performing a simulation by sweeping through a range of values and at predetermined intervals across said corners;

extracting data from said simulation; and

parsing and interpreting said data to produce at least one report.

2. The method as recited in claim 1 wherein said representative benchmark circuit is configured to represent one selected from the group consisting of:

a clock path,

a data path, and

a flip-flop path.

3. The method as recited in claim 1 wherein said sweeping occurs between slow and fast corners.

4. The method as recited in claim 1 wherein said sweeping occurs among various corners that define a safe zone.

5. The method as recited in claim 1 further comprising writing said data to a databank.

6. The method as recited in claim 1 wherein said at least one report is selected from the group consisting of:

a 3D analysis and contour plot,

a 2D analysis, and

a tables formed of said data.

7. The method as recited in claim 1 wherein said technology node is selected from the group consisting of:

a scale of a process employed to fabricate an integrated circuit,

a substrate material employed in said integrated circuit,

an interconnect material employed in said integrated circuit, and

a device type employed in said integrated circuit.

Assignments (9)