Semiconductor package with reduced inductive coupling between adjacent bondwire arrays
A semiconductor package ( 20 ) includes circuits ( 22, 24 ). The circuit ( 22 ) includes electrical devices ( 52, 54 ) interconnected by a bondwire array ( 62 ). Likewise, the circuit ( 24 ) includes electrical devices ( 58, 60 ) interconnected by a bondwire array ( 64 ). Signal wires ( 76 ) of the bondwire array ( 62 ) are proximate to signal wires ( 78 ) of the bondwire array ( 64 ). Ground wires ( 66, 68 ) are located on either side of, and close to, bondwire array ( 62 ). Ground wires ( 70, 72 ) are located on either side of, and close to, bondwire array ( 64 ). The ground wires ( 66, 68, 70,72 ) are electrically coupled to a ground region ( 74 ). The ground wires ( 66, 68, 70, 72 ) reduce a magnetic flux density ( 140 ) via induced return currents ( 126, 130 ) on the ground wires of opposite polarity to signal currents ( 124, 128 ) on the bondwire arrays ( 62, 64 ) to reduce inductive coupling between the adjacent bondwire arrays ( 62, 64 ).
1. A semiconductor package comprising:
a first circuit having a first electrical device, a second electrical device, and a first bondwire array of first wires interconnecting said first electrical device with said second electrical device;
a second circuit adjacent to said first circuit, said second circuit having a third electrical device, a fourth electrical device, and a second bondwire array of second wires interconnecting said third electrical device with said fourth electrical device, said second bondwire array being proximate to said first bondwire array; and
at least one ground wire located between said first and second bondwire arrays and arranged substantially aligned with one of said first bondwire array of said first wires and said second bondwire array of said second wires, said at least one ground wire being coupled to a ground region.
2. A semiconductor package as claimed in claim 1 wherein said one of said first bondwire array of said first wires and said second bondwire array of said second wires, and said at least one ground wire exhibit a substantially common profile.
3. A semiconductor package as claimed in claim 1 wherein:
said first bondwire array includes a first inner wire of said first wires, said first inner wire being closer to said second bondwire array than remaining ones of said first wires;
said second bondwire array includes a second inner wire of said second wires, said second inner wire being closer to said first bondwire array than remaining ones of said second wires; and
said at least one ground wire includes a first ground wire positioned proximate said first inner wire and a second ground wire positioned proximate said second inner wire.
4. A semiconductor package as claimed in claim 3 wherein:
each of said first wires of said first bondwire array and said first ground wire are attached to a first topside of said first electrical device; and
each of said second wires of said second bondwire array and said second ground wire are attached to a third topside of said third electrical device.
5. A semiconductor package as claimed in claim 4 wherein:
said each of said first wires of said first bondwire array and said first ground wire are further attached to a second topside of said second electrical device; and
said each of said second wires of said second bondwire array and said second ground wire are further attached to a fourth topside of said fourth electrical device.
6. A semiconductor package as claimed in claim 5 wherein:
a first ground interconnect is located on at least one of said first and second topsides of respective first and second electrical devices, said first ground wire being coupled to said first ground interconnect; and
a second ground interconnect is located on at least one of said third and fourth topsides of respective third and fourth electrical devices, said second ground wire being coupled to said second ground interconnect, and said first and second ground interconnects being electrically coupled with said ground region.
7. A semiconductor package as claimed in claim 3 wherein:
said first ground wire is spaced apart from said first inner wire by a distance; and
said second ground wire is spaced apart from said second inner wire by substantially said distance.
8. A semiconductor package as claimed in claim 7 wherein said distance is between 50 and 500 microns.
9. A semiconductor package as claimed in claim 3 wherein:
said first bondwire array includes a first outer wire of said first wires, said first outer wire being farther from said second bondwire array than remaining ones of said first wires;
said second bondwire array includes a second outer wire of said second wires, said second outer wire being farther from said first bondwire array than remaining ones of said second wires; and
said semiconductor package further comprises a third ground wire positioned proximate said first outer wire and a fourth ground wire positioned proximate said second outer wire, said third and fourth ground wires being coupled to said ground region.
10. A semiconductor package as claimed in claim 9 wherein:
said first ground wire is spaced apart from said first inner wire by a distance;
said second ground wire is spaced apart from said second inner wire by said distance;
said third ground wire is spaced apart from said first outer wire by said distance; and
said fourth ground wire is spaced apart from said second outer wire by said distance.
11. A semiconductor package as claimed in claim 9 wherein:
each of said first wires of said first bondwire array, said first ground wire, and said third ground wire exhibit a first substantially common profile; and
each of said second wires of said second bondwire array, said second ground wire, and said fourth ground wire exhibit a second substantially common profile.
12. A semiconductor package as claimed in claim 1 wherein said semiconductor package comprises a Doherty power amplifier, said first circuit is a carrier amplifier of said Doherty power amplifier, said second circuit is a peaking amplifier of said Doherty power amplifier, said first and third electrical devices are transistors, and said second and fourth electrical devices are capacitors.
13. A semiconductor package as claimed in claim 12 wherein said first and second circuits are mounted on a common carrier.
14. A Doherty power amplifier semiconductor package comprising:
a carrier amplifier having a first transistor, a first capacitor, and a first bondwire array of first wires interconnecting said first transistor with said first capacitor;
a peaking amplifier adjacent to carrier amplifier, said peaking amplifier having a second transistor, a second capacitor, and a second bondwire array of second wires interconnecting said second transistor with said second capacitor, said second bondwire array being proximate to said first bondwire array, said first bondwire array including a first inner wire of said first wires, said first inner wire being closer to said second bondwire array than remaining ones of said first wires, said second bondwire array including a second inner wire of said second wires, said second inner wire being closer to said first bondwire array than remaining ones of said second wires;
a first ground wire positioned proximate said first inner wire and substantially aligned with said first inner wire; and
a second ground wire positioned proximate said second inner wire and substantially aligned with said second inner wire, said first and second ground wires being located between said first and second bondwire arrays, said first and second ground wires being coupled to a ground region.
15. A Doherty power amplifier semiconductor package as claimed in claim 14 wherein:
said first bondwire array includes a first outer wire of said first wires, said first outer wire being farther from said second bondwire array than remaining ones of said first wires;
said second bondwire array includes a second outer wire of said second wires, said second outer wire being farther from said first bondwire array than remaining ones of said second wires; and
said Doherty power amplifier semiconductor package further comprises a third ground wire positioned proximate said first outer wire and a fourth ground wire positioned proximate said second outer wire, said third and fourth ground wires being coupled to said ground region.
16. A Doherty power amplifier semiconductor package as claimed in claim 15 wherein:
said first ground wire is spaced apart from said first inner wire by a distance;
said second ground wire is spaced apart from said second inner wire by said distance;
said third ground wire is spaced apart from said first outer wire by said distance; and
said fourth ground wire is spaced apart from said second outer wire by said distance, said distance being between 50 and 500 microns.
17. A Doherty power amplifier semiconductor package as claimed in claim 15 wherein:
each of said first wires of said first bondwire array, said first ground wire, and said third ground wire exhibit a first substantially common profile; and
each of said second wires of said second bondwire array, said second ground wire, and said fourth ground wire exhibit a second substantially common profile.
18. A semiconductor package comprising:
a first circuit having a first electrical device, a second electrical device, and a first bondwire array interconnecting said first electrical device with said second electrical device;
a second circuit adjacent to said first circuit, said second circuit having a third electrical device, a fourth electrical device, and a second bondwire array interconnecting said third electrical device with said fourth electrical device, said second bondwire array being proximate to said first bondwire array with first wires of said first bondwire array being arranged substantially aligned with second wires of said second bondwire array, said first bondwire array including a first inner wire of said first wires, said first inner wire being closer to said second bondwire array than remaining ones of said first wires, said second bondwire array including a second inner wire of said second wires, said second inner wire being closer to said first bondwire array than remaining ones of said second wires;
a first ground wire positioned proximate said first inner wire, each of said first wires of said first bondwire array and said first ground wire exhibiting a first substantially common profile; and
a second ground wire positioned proximate said second inner wire, each of said second wires of said second bondwire array and said second ground wire exhibiting a second substantially common profile, said first and second ground wires being located between said first and second bondwire arrays, and said first and second ground wires being coupled to a ground region.
19. A semiconductor package as claimed in claim 18 wherein:
said each of said first wires of said first bondwire array and said first ground wire are attached to a first topside of said first electrical device; and
said each of said second wires of said second bondwire array and said second ground wire are attached to a third topside of said third electrical device.
20. A semiconductor package as claimed in claim 19 wherein:
said each of said first wires of said first bondwire array and said first ground wire are further attached to a second topside of said second electrical device; and
said each of said second wires of said second bondwire array and said second ground wire are further attached to a fourth topside of said fourth electrical device.