Method for manufacturing N-type and P-type chalcogenide material, doped homojunction chalcogenide thin film transistor and method of fabricating the same
View Patent ↗The present invention provides a doped homojunction chalcogenide thin film transistor and a method of fabricating the same, comprising forming an N-type chalcogenide layer constituting a channel layer on a substrate, forming and patterning a diffusion prevention layer on the upper part of the N-type chalcogenide layer, and forming a P-type chalcogenide layer constituting source and drain regions by depositing and diffusing Te alloy on the N-type chalcogenide layer. With the present invention, a thin film transistor can be fabricated using chalcogenide material having N-type conductivity and chalcogenide material having P-type conductivity.
1. A thin film transistor, comprising:
an oxygen and GeTe doped chalcogenide layer forming a channel layer and constituting a first type conductivity;
an oxygen doped chalcogenide layer formed at both sides of the chalcogenide layer having the first type conductivity to constitute source and drain regions and having a second type conductivity; and
source and drain electrodes connected to the chalcogenide layer constituting the source and drain regions and having the second conductivity.
2. The thin film transistor according to claim 1 , wherein the chalcogenide layer constituting the channel layer and the source and drain regions is a Ge 2 Sb 2 Te 5 layer.
3. The thin film transistor according to claim 1 , further comprising:
a gate electrode formed by interposing a gate dielectric at the bottom of the chalcogenide layer having the first conductivity.
4. The thin film transistor according to claim 3 , wherein the gate dielectric is a polymer PMMA film that is an organic material.
5. The thin film transistor according to claim 3 , wherein the gate dielectric is a silicon oxide film formed using a PECVD method.
6. The thin film transistor according to claim 1 , wherein a diffusion prevention layer is formed on the upper part of the chalcogenide layer having the first conductivity.
7. The thin film transistor according to claim 1 , wherein the channel layer is P-type, and the source and drain regions are N-type.
8. A thin film transistor comprising:
an oxygen doped chalcogenide layer forming a channel layer and constituting a first type conductivity;
an oxygen and GeTe doped chalcogenide layer formed at both sides of the oxygen doped chalcogenide layer having the first type conductivity to constitute source and drain regions and having a second type conductivity; and
source and drain regions and having the second type conductivity.
9. The thin film transistor according to claim 8 , wherein the chalcogenide layer constituting the channel layer and the source and drain regions is a Ge 2 Sb 2 Te 5 layer.
10. The thin film transistor according to claim 8 , further comprising:
a gate electrode formed by interposing a gate dielectric at the bottom of the oxygen doped chalcogenide layer having the first type conductivity.
11. The thin film transistor according to claim 10 , wherein the gate dielectric is a polymer PMMA film that is an organic material.
12. The thin film transistor according to claim 10 , wherein the gate dielectric is a silicon oxide film formed using a PECVD method.
13. The thin film transistor according to claim 8 , wherein a diffusion prevention layer is formed on the upper part of the oxygen doped chalcogenide layer having the first type conductivity.