Semiconductor storage device including a lever shift unit that shifts level of potential of bit line pair
A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BL B when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.
1. A semiconductor storage device comprising:
a memory cell array in which a plurality of memory cells storing data are arranged;
a plurality of word lines that selectively drive one of the memory cells in the memory cell array;
a plurality of pairs of bit lines that transmit/receive data to/from the memory cell that is selected;
a precharge circuit that precharges a bit line pair to about half of a power supply potential by equalizing potential of the bit line pair;
a sense amplifier that is provided in accordance with each of the bit line pairs; and
a level shift unit that shifts level of potential of the bit lines when the sense amplifier starts to read potential of the bit line pair, wherein
the level shift unit comprises:
level shifting capacitors, each of which having one electrode connected to each bit line, and forming one pair by two level shifting capacitors for each bit line pair; and
a timing generator that is connected to each of the other electrodes of the level shifting capacitors in common, supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.
2. The semiconductor storage device according to claim 1 , wherein an activation period of the shift capacitor drive signal by the timing generator is immediately before a memory cell selection signal is activated.
3. The semiconductor storage device according to claim 1 , wherein an activation period of the shift capacitor drive signal by the timing generator is immediately before the sense amplifier is activated.
4. The semiconductor storage device according to claim 1 , wherein
the level shift unit executes reallocation of charge between the bit line pair after precharge operation and the level shifting capacitor to shift potential level of the bit line pair, so as to make gate bias of the sense amplifier at a time of starting reading larger than at least half of power supply potential.
5. The semiconductor storage device according to claim 4 , comprising reducing a bias level of the sense amplifier at a time of starting reading to a ground level by combination of values of capacitance of the level shifting capacitor, voltage of the sense amplifier activation signal, and counter voltage of the level shifting capacitor.