Bonded semiconductor structure and method of making the same
A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line. The memory circuit includes a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack is coupled to the interconnect region through a bonding interface, and wherein the semiconductor layer stack includes a pn junction.
1. A bonded semiconductor structure static random access memory circuit, comprising:
a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line; and
a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack is coupled to the interconnect region through a bonding interface, and wherein the semiconductor layer stack includes a pn junction.
2. The circuit of claim 1 , further including a conductive bonding layer which extends between the interconnect region and stack of semiconductor layers.
3. The circuit of claim 2 , further including a second horizontally oriented transistor carried by the support substrate, wherein the first and second horizontally oriented transistors are in communication with each other through the conductive bonding layer.
4. The circuit of claim 1 , wherein a source and control terminal of the first horizontally oriented transistor are in communication with each other through the conductive bonding layer.
5. The circuit of claim 1 , wherein the support substrate includes a single substrate well region per SRAM unit cell.
6. The circuit of claim 1 , further including the detach region, wherein the detach region includes porous silicon.
7. A method of manufacturing a bonded semiconductor structure static random access memory circuit, comprising:
providing a support substrate which carries a first type of transistor;
providing a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack includes a pn junction;
coupling the semiconductor layer stack to the support substrate through a bonding interface; and
processing the semiconductor layer stack to form a second type of transistor.
8. The method of claim 7 , further including providing an interconnect region which is carried by the support substrate, the interconnect region having a conductive line.
9. The method of claim 7 , further including providing the first and second types of transistors so they are NMOS and PMOS transistors, respectively.
10. The method of claim 7 , further including providing the first and second types of transistors so they are in communication with each other through the bonding interface.
11. The method of claim 7 , wherein the first and second types of transistors are horizontally and vertically oriented transistors, respectively.
12. The method of claim 7 , further including forming a single substrate well region per SRAM unit cell.
13. The method of claim 7 , further including separating the donor substrate from the semiconductor layer stack.
14. A bonded semiconductor structure static random access memory circuit, comprising:
a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line; and
a first mesa structure coupled to the interconnect region through a first bonding interface, wherein the first mesa structure includes a pn junction.
15. The circuit of claim 14 , further including a first conductive bonding contact region which extends between the interconnect region and first mesa structure.
16. The circuit of claim 15 , further including a second horizontally oriented transistor, wherein the first and second horizontally oriented transistors are connected to the first conductive bonding contact region.
17. The circuit of claim 14 , wherein the first mesa structure and first horizontally oriented transistor are in communication with each other through the first bonding interface.
18. The circuit of claim 14 , further including a second mesa structure coupled to the interconnect region through a second bonding interface, wherein the second mesa structure includes a pn junction.
19. The circuit of claim 18 , further including a second conductive bonding contact region which extends between the interconnect region and second mesa structure.
20. The circuit of claim 14 , wherein the support substrate includes a single substrate well region per SRAM unit cell.