Die-warpage compensation structures for thinned-die devices, and methods of assembling same
A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die.
1. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface, wherein the metal wiring interconnect layout has a metallic thickness from 5 micrometer (μm) to 15 μm; and
a back-side lamination (BSL) disposed on the thinned backside, wherein the BSL includes a second thickness that is less than the first thickness, and wherein the BSL resists warpage of the microelectronic die to less than 10 μm.
2. The apparatus of claim 1 , wherein the microelectronic die first thickness is from greater than 50 μm to 400 μm, and wherein the BSL second thickness is in a range from 4 μm to 50 μm.
3. The apparatus of claim 1 , wherein the microelectronic die first thickness is from greater than 50 μm to 400 μm, wherein the BSL second thickness is in a range from 4 μm to 50 μm;
wherein the active surface further includes between 1 and 8 levels of metallization wiring disposed between the metal wiring interconnect layout and the active surface.
4. The apparatus of claim 1 , wherein the BSL resists warpage of the microelectronic die by less than 10 μm and wherein the BSL resists warpage due to passive rigidity of the BSL, and wherein the BSL includes a sculptured topology that is complementary to the metal wiring interconnect layout.
5. The apparatus of claim 1 , wherein the BSL resists warpage of the microelectronic die, and wherein the BSL resists warpage due to a sculptured topology that is complementary to the metal wiring interconnect layout.
6. The apparatus of claim 1 , wherein the BSL resists warpage of the microelectronic die due to rigidity that is counteractive to the metal wiring interconnect layout.
7. The apparatus of claim 1 , wherein the BSL resists warpage of the microelectronic die due to rigidity that is counteractive to the metal wiring interconnect structure, wherein the BSL is patterned to counter thermal expansion of the metal wiring interconnect structure.
8. The apparatus of claim 1 , wherein the BSL resists warpage of the microelectronic die wherein the BSL is mirror-image patterned counter to the metal wiring interconnect structure.
9. The apparatus of claim 1 , wherein the BSL resists warpage of the microelectronic die due to rigidity that is counteractive to metal wiring interconnect structure, and wherein the BSL is mirror-image patterned counter to the metal wiring interconnect structure.
10. The apparatus of claim 1 , wherein the BSL includes a filler.
11. The apparatus of claim 1 , wherein the BSL includes a homogeneously dispersed filler.
12. The apparatus of claim 1 , wherein the BSL includes an anisotropically aligned filler.
13. The apparatus of claim 1 , wherein the BSL includes a homogeneously dispersed and anisotropically aligned filler.
14. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
a dummy wiring layout disposed against the thinned backside, wherein the dummy wiring layout is configured to be complementary to the metal wiring interconnect layout, wherein the dummy wiring layout is mirror-image patterned to match the metal wiring interconnect layer, and wherein the dummy wiring layout is counter-active to the metal wiring interconnect layout under a heat load.
15. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
a dummy wiring layout disposed against the thinned backside, wherein the dummy wiring layout is configured to be complementary to the metal wiring interconnect layout, the apparatus further including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout.
16. The apparatus of claim 15 , wherein the metal wiring interconnect layout includes at least a first layout sector, a second layout sector, and a third layout sector, the apparatus further including, wherein the patterned backside lamination is about the same thickness as the dummy wiring layout, and wherein the patterned backside lamination is patterned as a first patterned sector, a second patterned sector, and a third patterned sector, which vertically correspond to the first- second- and third layout sectors, respectively.
17. The apparatus of claim 15 , wherein the patterned backside lamination includes a filler.
18. The apparatus of claim 15 , wherein the patterned backside lamination includes a homogeneously dispersed filler.
19. The apparatus of claim 15 wherein the patterned backside lamination includes an anisotropically aligned filler.
20. The apparatus of claim 15 , wherein the patterned backside lamination includes a homogeneously dispersed and anisotropically aligned filler.
21. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the metal wiring interconnect layout includes at least a first layout sector, a second layout sector, and a third layout sector, the apparatus further including a patterned backside lamination that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination is about the same thickness as the dummy wiring layout, and wherein the patterned backside lamination is patterned as a first patterned sector, a second patterned sector, and a third patterned sector, which vertically correspond to the first- second- and third layout sectors, respectively.
22. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination includes a sculptured topology.
23. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination includes a sculptured topology with at least one conical-shaped depression.
24. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination includes a sculptured topology with at least one curve-shaped depression.
25. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination includes a filler.
26. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination includes a homogeneously dispersed filler.
27. An apparatus comprising:
a microelectronic die including a first thickness, wherein the die exhibits a thinned backside, an active surface;
a metal wiring interconnect layout disposed on the active surface; and
including a patterned backside lamination that includes a sculptured topology that is complementary to the metal wiring interconnect layout, wherein the patterned backside lamination includes an anisotropically aligned filler.
28. The apparatus of claim 27 , wherein the patterned backside lamination includes a homogeneously dispersed filler.