Storage device including a memory cell having multiple memory layers

1. A storage device comprising:

a controller; and

a plurality of resistive elementary memory cells accessible via the controller, each resistive elementary memory cell of the plurality of resistive elementary memory cells including a plurality of memory layers, wherein each of the plurality of memory layers has a different critical voltage for changing a polarization of the memory layer.

2. The storage device of claim 1 , wherein the plurality of memory layers has different critical voltages because of different hysteretic properties of the memory layers.

3. The storage device of claim 1 , further comprising a plurality of electrode layers associated with the plurality of memory layers, wherein each memory layer of the plurality of memory layers is separated from an adjacent memory layer by an electrode layer of the plurality of electrode layers.

4. The storage device of claim 3 , wherein the plurality of electrode layers comprises symmetric electrode layers.

5. The storage device of claim 3 , wherein the plurality of electrode layers comprises asymmetric electrode layers, and the asymmetric electrode layers provide the different critical voltages of the memory layers.

6. The storage device of claim 1 , wherein a selected resistive elementary memory cell of the plurality of resistive elementary memory cells stores multiple data values that are represented by a unique tunneling resistance.

7. The storage device of claim 6 , wherein the controller is adapted to apply a unique write signal to the selected resistive elementary memory cell to alter the unique tunneling resistance to represent different data values.

8. The storage device of claim 1 , wherein the plurality of memory layers comprises non-magnetic memory layers.

9. The storage device of claim 1 , wherein the plurality of memory layers are selected to have a hysteretic property including a spontaneous polarization property.

10. A memory device comprising:

a first electrode;

a second electrode;

multiple memory layers between the first and second electrodes to store multiple data values, each memory layer of the multiple memory layers having a unique hysteretic property to store a data value of the multiple data values; ; and

a controller coupled to the multiple memory layers via at least one of the first and second electrodes, the controller to read the multiple data values from the multiple memory layers without altering the multiple data values.

11. The memory device of claim 10 , wherein the multiple memory layers comprise ferroelectric layers adapted to carry independent polarized electrical fields to induce electron charge distributions representing unique data values.

12. The memory device of claim 10 , wherein the multiple memory layers comprise phase change media layers having hysteretic properties that can be independently configured to represent unique data values.

13. The memory device of claim 10 , wherein the multiple memory layers comprise charge trap layers to trap electrical charges, the charge trap layers configurable to induce an electron charge distribution to represent unique data values.

14. The memory device of claim 10 , wherein the multiple data values are represented by a unique tunneling resistance through the multiple memory layers.

15. The memory device of claim 10 , further comprising multiple internal electrodes corresponding to the multiple memory layers, wherein adjacent memory layers of the multiple memory layers are separated by an internal electrode of the multiple internal electrodes.

16. The memory device of claim 15 , further comprising multiple insulator layers corresponding to the multiple internal electrodes, wherein a multiple insulator layer of the multiple insulator layers separates the internal electrode from a memory layer of the adjacent memory layers.

17. A memory device comprising:

a plurality of resistive memory cells, each resistive memory cell including multiple stacked memory layers to store multiple data values, each memory layer of the multiple stacked memory layers having an unique hysteretic property configurable to represent a unique data value; and

a controller having access to the plurality of resistive memory cells, the controller adapted to select a resistive memory cell of the plurality of resistive memory cells, the controller to read and to write data from and to a selected memory layer of the selected resistive memory cell.

18. The memory device of claim 17 , wherein the controller is adapted to configure a hysteretic property of the selected memory layer by applying a voltage at a selected voltage level that is associated with the selected memory layer.

19. The memory device of claim 17 , further comprising a plurality of internal electrodes separating adjacent memory layers of the multiple stacked memory layers.

20. The memory device of claim 17 , wherein the plurality of internal electrodes are formed from a semiconductor material.

21. Original) The memory device of claim 20 , wherein a first doping concentration of a first internal electrode of the plurality of internal electrodes is different from a second doping concentration of a second internal electrode of the plurality of internal electrodes.

22. The memory device of claim 20 , wherein each internal electrode of the plurality of internal electrodes has a unique conductance within the selected resistive memory cell.

23. The memory device of claim 20 , wherein the plurality of internal electrodes comprises a conductive metal.

24. The memory device of claim 20 , further comprising a plurality of insulator layers, each insulator layer of the plurality of insulator layers associated with a respective internal electrode of the plurality of internal electrodes.

25. The memory device of claim 24 , wherein insulator layers of the plurality of insulator layers have different insulator properties, and wherein internal electrodes of the plurality of internal electrodes have different electrical properties.

26. The storage device according to claim 1 , wherein the different critical voltages can be due to the plurality of memory layers comprising different materials, the plurality of memory layers comprising different compositions of the same materials, the plurality of memory layers having different thicknesses, materials adjacent to the plurality of memory layers, the plurality of memory layers having different thicknesses of materials therebetween, the plurality of memory layers having different types of layers therebetween, or combinations thereof.