IP Library › Granted Patent US 8,117,400
Granted Patent B2
US 8,117,400 · App. 12/446,413 · Granted Feb 14, 2012

System and method for fetching an information unit

Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,117,400
App. No.
12/446,413
Granted
Feb 14, 2012
Kind
B2
Abstract

A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

Claims (31)

1. A method for fetching an information unit, the method comprises:

receiving a request to execute a write through cacheable operation of the information unit;

emptying a fetch unit of data stored at the fetch unit, wherein the fetch unit is coupled to a cache module and to a high level memory unit;

receiving at the cache module an indication that the fetch unit is empty;

determining, in response to receiving the indication that the fetch unit is empty, whether the cache module stores an older version of the information unit; and

selectively writing the information unit to the cache module in response to the determination.

2. The method according to claim 1 wherein the emptying comprises:

completing an execution of currently executed speculative fetch operations and delaying an execution of requested speculative fetch operations that were not started.

3. The method according to claim 1 wherein the emptying comprises:

sending to an arbiter that controls an access to the high level memory unit, a write through request;

wherein the write through request has a higher priority than requests to perform speculative fetch operations.

4. The method according to claim 1 wherein the selective writing also comprises writing the information unit from a write through buffer to the high level memory unit.

5. The method according to claim 1 wherein the receiving the request to execute a write through cacheable operation is followed by determining whether to empty the fetch unit of data stored at the fetch unit before determining whether the cache module stores a version of the information unit.

6. The method according to claim 5 wherein the determining whether to empty the fetch unit comprises comparing an address of the information unit to a predefined range of addresses.

7. The method according to claim 1 wherein the selectively writing is followed by completing an execution of a delayed fetch operation.

8. A device adapted to fetch an information unit, the device comprises:

a processor adapted to generate a request to execute a write through cacheable operation of the information unit;

a cache module adapted to receive an indication that a fetch unit is empty, and in response to receiving the indication that the fetch unit is empty, determine whether the cache module stores an older version of the information unit and selectively store the information unit in response to the determination; and

an arbiter adapted to empty the fetch unit;

wherein the fetch unit is coupled to the cache module and to a high level memory.

9. The device according to claim 8 wherein the arbiter is adapted to complete an execution of currently executed speculative fetch operations and to delay an execution of requested speculative fetch operations that were not started.

10. The device according to claim 8 wherein the device is adapted to send to the arbiter a write through request wherein the write through request has a higher priority than requests to perform speculative fetch operations.

11. The device according to claim 8 wherein the device comprises a write through buffer adapted to generate requests to write the information unit to the high level memory unit.

12. The device according to claim 8 wherein the device is adapted to determine whether to empty the fetch unit from data before determining whether the cache module stores a version of the information unit.

13. The device according to claim 12 wherein the device is adapted to compare between an address of the information unit and between a predefined address range and in response determine whether to empty the fetch unit from data before determining whether the cache module stores a version of the information unit.

14. The device according to claim 8 wherein the device is adapted to complete an execution of a delayed fetch operation.

15. The method according to claim 2 wherein the emptying comprises:

sending, to an arbiter that controls an access to the high level memory unit, a write through request;

wherein the write through request has a higher priority than requests to perform speculative fetch operations.

16. The method according to claim 2 wherein the selective writing also comprises writing the information unit from a write through buffer to the high level memory unit.

17. The method according to claim 3 wherein the receiving the request to execute a write through cacheable operation is followed by determining whether to empty the fetch unit of data stored at the fetch unit before determining whether the cache module stores a version of the information unit.

Assignments (23)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2026
From: NXP USA, INC.
To: LOCK SEMICONDUCTOR LLC
Reel/Frame 074369/0197 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0823 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Sep 23, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023273/0099 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2009
From: ZAMSKY, ZVI; ANSCHEL, MOSHE; ELDAR, ALON; FLAT, DMITRY; GODIN, KOSTANTIN; PELED, ITAY; PELEG, DVIR
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 023034/0979 →
Continuity (1)
Related Publication 20100325366A1 · Dec 23, 2010