IP Library › Granted Patent US 8,119,928
Granted Patent B2
US 8,119,928 · App. 12/343,844 · Granted Feb 21, 2012

Multi-layered wiring substrate and method of manufacturing the same

Assignee: NEC Corporation
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Quick Facts
Patent No.
US 8,119,928
App. No.
12/343,844
Granted
Feb 21, 2012
Kind
B2
Abstract

In a multi-layered wiring substrate according to an exemplary aspect of the present invention, a conductor formed in an edge face area functions as a pad for mounting a connector.

Claims (18)

1. A multi-layered wiring substrate, comprising:

a through hole formed on a cutting plane line of the multi-layered wiring substrate and cut off along with the cutting plane line to expose an inner wall face of the through hole in an edge face area of an edge face of the multi-layered wiring substrate formed by cutting the multi-layered wiring substrate along the cutting plane line from a first edge face of the multi-layered wiring substrate to a second edge face of the multi-layered wiring substrate opposed to the first edge face; and

a conductor formed in the inner wall face of the through hole and functioning as a pad for mounting a connector.

2. The multi-layered wiring substrate according to claim 1 , wherein the pad is divided into a plurality of parts.

3. The multi-layered wiring substrate according to claim 1 , wherein a counter-bored portion is formed along with a periphery of the through hole.

4. The multi-layered wiring substrate according to claim 2 , wherein a counter-bored portion is formed along with a periphery of the through hole.

5. The multi-layered wiring substrate according to claim 1 , wherein the conductor includes first and second spaced apart pads divided therefrom in the inner wall face of the through hole.

6. The multi-layered wiring substrate according to claim 1 , wherein a base material of the multi-layered wiring substrate has a front surface and a rear surface opposed thereto and an inner layer having a signal pattern disposed internally within the base material and parallel to the front and rear surfaces, wherein the conductor is formed connected to the inner layer.

7. An assembly including the multi-layered wiring substrate according to claim 6 , and a capacitor mounted across the pads.

8. A method of manufacturing a multi-layered wiring substrate, the method comprising:

forming a through hole on a cutting plane line of the multi-layered wiring substrate of a base material;

forming a conductor in an inner wall face of the through hole;

forming cutouts in the conductor near the cutting plane line of the multi-layered wiring substrate, thereby to form at least two separate conductors from said conductor;

and

cutting the base material along the cutting plane line of the multi-layered wiring substrate and employing the conductor separate conductors formed in an edge face area of the multi-layered wiring substrate as pads for mounting conductors.

9. The method of manufacturing the multi-layered wiring substrate according to claim 8 , wherein a counter-bored portion is formed along with a periphery of the through hole after forming the conductor in the inner wall face of the through hole.

10. The method of manufacturing the multi-layered wiring substrate according to claim 8 , wherein a base material of the multi-layered wiring substrate has a front surface and a rear surface opposed thereto and an inner layer having a signal pattern disposed internally within the base material and parallel to the front and rear surfaces, wherein the step of forming the conductor forms the conductor to contact the inner layer.

11. A method of manufacturing an assembly including manufacturing the multi-layered wiring substrate according to claim 8 , further comprising mounting a capacitor across the pads.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2008
From: MATSUI, ISAO
To: NEC CORPORATION
Reel/Frame 022028/0103 →
Priority Claims (1)
JP 2007-338859 · Dec 28, 2007 · national
Continuity (1)
Related Publication 20090166078A1 · Jul 2, 2009