Method to deposit conformal low temperature SiO2
Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
1. A method of depositing a conformal silicon dioxide in semiconductor fabrication comprising:
positioning a semiconductor substrate having a sacrificial material adjacent the semiconductor substrate into a deposition region of a deposition apparatus, the semiconductor substrate having a non-planar topography;
exposing the semiconductor substrate to a first mixture comprising a first reactant and a first catalyst wherein the first reactant is hexachlorodisilane (“HCD”) and the first catalyst is pyridine, permitting the formation of a first reactant chemisorbed layer on the semiconductor substrate; and
exposing the semiconductor substrate to a second mixture comprising a second reactant and a second catalyst wherein the second reactant is a compound containing oxygen and hydrogen and the second catalyst is pyridine, permitting the formation of a silicon dioxide monolayer on the semiconductor substrate; wherein the exposings of the semiconductor substrate to the first mixture and the second mixture do not decompose the sacrificial material.
2. The method of claim 1 , further comprising:
exposing the semiconductor substrate to the first reactant and first catalyst;
removing excess first reactant and first catalyst from the deposition region;
purging the deposition region with inert gas;
exposing the semiconductor substrate to the second reactant and second catalyst;
removing excess second reactant and second catalyst from the deposition region; and
purging the deposition region with inert gas.
3. The method of claim 1 , wherein the exposings of the semiconductor substrate to the first mixture and the second mixture are is performed at a temperature in a range of about 30° C. to about 90° C.
4. The method of claim 1 wherein the exposings of the semiconductor substrate to the first mixture and the second mixture are is performed at a temperature in a range of about 65° C. to about 80° C.
5. The method of claim 1 , wherein the deposition region of the deposition apparatus internal temperature is equalized to a temperature in a range of about 30° C. to about 90° C. prior to the exposings of the semiconductor substrate to the first mixture and second mixture.
6. The method of claim 1 , wherein the deposition region of the deposition apparatus internal temperature is equalized to a temperature in a range of about 65° C. to about 80° C. prior to the exposings of the semiconductor substrate to the first mixture and second mixture.
7. The method of claim 1 , wherein the deposition region of the deposition apparatus internal temperature is equalized to a temperature in a range of about 30° C. to about 32° C. prior to the exposings of the semiconductor substrate to the first mixture and second mixture.
8. The method of claim 1 , wherein the first reactant and first catalyst are introduced into the deposition region of the deposition apparatus at a temperature in a range of about 10° C. to about 90° C.
9. The method of claim 1 , wherein the first reactant and first catalyst are introduced into the deposition region of the deposition apparatus at a temperature in a range of about 20° C. to about 60° C.
10. The method of claim 1 , wherein the second reactant and second catalyst are introduced into the deposition region of the deposition apparatus at a temperature in a range of about 10° C. to about 90° C.
11. The method of claim 1 , wherein the second reactant and second catalyst are introduced into the deposition region of the deposition apparatus at a temperature in a range of about 20° C. to about 60° C.
12. The method of claim 1 , wherein the first reactant and first catalyst are introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 standard liters per minute (“slm”) to about 2.0 slm.
13. The method of claim 1 , wherein the first reactant is introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 slm to about 0.6 slm.
14. The method of claim 1 , wherein the first catalyst is introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 slm to about 0.75 slm.
15. The method of claim 1 , wherein the second reactant is introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 slm to about 3.0 slm.
16. The method of claim 1 , wherein the second reactant is introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 slm to about 2.0 slm.
17. The method of claim 1 , wherein the second catalyst is introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 slm to about 2.0 slm.
18. The method of claim 1 , wherein the second catalyst is introduced into the deposition region of the deposition apparatus at a rate in a range of about 0.1 slm to about 0.8 slm.
19. The method of claim 1 , wherein the depositing a conformal silicon dioxide is performed for approximately 20 to 610 seconds per cycle.
20. The method of claim 1 , wherein the depositing a conformal silicon dioxide is performed for approximately 65 to 125 seconds per cycle.
21. The method of claim 1 , wherein the sacrificial material adjacent the semiconductor substrate is transparent carbon.
22. The method of claim 1 , wherein the sacrificial material adjacent the semiconductor substrate is photoresist.