Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof
View Patent ↗The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit. The present invention can effectively reduce area the device occupies; it is applicable to the non-volatile memory field, realizing high-voltage output during a high-voltage operation and fast decoding output during a normal-voltage operation.
1. A decoding circuit withstanding a high voltage via a low-voltage MOS transistor, the decoding circuit comprising two CMOS inverters connected serially; wherein the decoding circuit further includes four switches, all being provided with one common terminal, two connection terminals and one control terminal;
the substrate of a PMOS transistor (MP 1 ) of the first CMOS inverter is connected with the substrate of a PMOS transistor (MP 2 ) of the second CMOS inverter and the common terminal of the second switch (KA 2 ), whose two connection terminals are power source VCC and ground VSS, respectively;
the source of the PMOS transistor (MP 1 ) of the first CMOS inverter is connected with the source of the PMOS transistor (MP 2 ) of the second CMOS inverter and the common terminal of the first switch (KA 1 ), whose two connection terminals are floating and power source VCC, respectively;
the source and the substrate of an NMOS transistor (MN 1 ) of the first CMOS inverter are connected with the common terminal of the third switch (KA 3 ), whose two connection terminals are connected with a half negative high voltage and the ground, respectively; and
the source and the substrate of an NMOS transistor (MN 2 ) of the second CMOS inverter are connected with the common terminal of the fourth switch (KA 4 ), whose two connection terminals are connected with the negative high voltage and the ground, respectively.
2. The decoding circuit withstanding the high voltage via the low-voltage MOS transistor according to claim 1 , wherein the decoding circuit further includes a sequence generation circuit for controlling the control terminals of the four switches.
3. The decoding circuit withstanding the high voltage via the low-voltage MOS transistor according to claim 1 , wherein the half negative high voltage and the negative high voltage are generated by a charge pump circuit.
4. A memory circuit comprising
a memory cell array;
wherein the memory circuit further includes the decoding circuit according to claim 1 , which decodes an address signal generated by a pre decoder and drives a word line of a memory cell in the memory cell array.
5. The memory circuit according to claim 4 , wherein in programming mode, with input of the first CMOS inverter being the ground, the substrate of the PMOS transistor in the two CMOS inverters is switched to the ground and the source to floating from the power source; the substrate and the source of the NMOS transistor in the first CMOS inverter are switched to the half negative high voltage from the ground, and the substrate and the source of the NMOS transistor in the second CMOS inverter are switched to the negative high voltage, with output of the second CMOS inverter, i.e. word line output of a decoder, being the negative high voltage.
6. The memory circuit according to claim 4 , wherein the control terminal of the four switches is controlled by the sequence generation circuit.