Manufacturing method of micro electronic mechanical system structure
A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.
1. A method of manufacturing a micro electronic mechanical system structure, comprising:
providing a substrate, wherein the substrate has a plurality of conductive regions;
forming a dielectric layer on the substrate;
forming a plurality of openings and a plurality of recesses in the dielectric layer, wherein the openings expose the conductive regions, and the recesses are located between the openings;
forming a conductive layer on the dielectric layer, and filling the openings and the recesses with the conductive layer;
patterning the conductive layer to form a plurality of strips of first conductive patterns on the dielectric layer and to form a second conductive pattern on a sidewall and a bottom of each of the recesses, wherein the first conductive patterns are connected with each other through the second conductive patterns;
removing the dielectric layer; and
removing the second conductive patterns between the first conductive patterns.
2. The method of claim 1 , wherein a step of patterning the conductive layer comprises:
forming a hard mask layer on the conductive layer, the hard mask layer at least covering a portion of the conductive layer located in the recesses;
performing an etching process with the hard mask layer as a mask; and
removing the hard mask layer.
3. The method of claim 1 , wherein a step of removing the dielectric layer comprises a wet etching process.
4. The method of claim 1 , wherein a step of removing the second conductive patterns between the first conductive patterns comprises a dry etching process.
5. The method of claim 1 , wherein a material of the conductive layer comprises doped poly-silicon.
6. The method of claim 1 , wherein a material of the dielectric layer comprises oxide.
7. The method of claim 1 , before forming the dielectric layer, further comprising forming a passivation layer on the substrate.
8. The method of claim 7 , wherein a material of the passivation layer comprises nitride.
9. A method of manufacturing a micro electronic mechanical system structure, comprising:
providing a substrate, wherein the substrate has a plurality of conductive regions;
forming a dielectric layer on the substrate;
forming a plurality of openings and a trench in the dielectric layer, wherein the openings expose the conductive regions, and the trench is located between the openings;
forming a connective layer in the trench;
forming a conductive layer on the dielectric layer and the connective layer, and filling the openings with the conductive layer;
patterning the conductive layer to form a plurality of strips of conductive patterns on the dielectric layer and the connective layer, wherein the conductive patterns are connected with each other through the connective layer;
removing the dielectric layer; and
removing the connective layer between the conductive patterns.
10. The method of claim 9 , wherein a material of the connective layer is different from a material of the dielectric layer.
11. The method of claim 9 , wherein a material of the connective layer comprises an insulation material or a conductive material.
12. The method of claim 9 , wherein a material of the connective layer comprises silicon nitride, silicon carbide or poly-silicon.
13. The method of claim 9 , wherein a material of the connective layer is identical to a material of the conductive layer, and a step of forming the connective layer and a step of forming the conductive layer are performed simultaneously.
14. The method of claim 9 , wherein the trench extends from a surrounding of one of the openings to a surrounding of another one of the openings.
15. The method of claim 9 , wherein a step of removing the dielectric layer comprises a wet etching process.
16. The method of claim 9 , wherein a step of removing the connective layer between the conductive patterns comprises a dry etching process.
17. The method of claim 9 , wherein a material of the conductive layer comprises doped poly-silicon.
18. The method of claim 9 , wherein a material of the dielectric layer comprises oxide.
19. The method of claim 9 , before forming the dielectric layer, further comprising forming a passivation layer on the substrate.
20. The method of claim 19 , wherein a material of the passivation layer comprises nitride.