Forming seal ring in an integrated circuit die
View Patent ↗The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
1. A method of forming a semiconductor device, the method comprising:
forming one or more semiconductor devices in an active circuit region of a first semiconductor die;
forming one or more inter-metal dielectric (IMD) layers over a front-side surface of the first semiconductor die;
forming interconnect metal features in the active circuit region, the interconnect metal features being coupled to the one or more semiconductor devices and being formed in respective ones of the one or more IMD layers;
forming a seal ring in the one or more IMD layers, the seal ring enclosing the interconnect metal features in the active circuit region;
forming a recess in the one or more IMD layers and in the first semiconductor die, after the formation of the seal ring, the recess being separated from the active circuit region by the seal ring; and
filling the recess with conductive material, thereby forming a through-silicon via (TSV).
2. The method of claim 1 , wherein the seal ring comprises a plurality of stacked metal, rings in a plurality of interconnect metal layers in the one or more IMD layers, the respective stacked metal rings being connected together through one or more via.
3. The method of claim 1 , wherein the seal ring has a shape selected from a group consisting of a square, a rectangle, a polygon, a continuous curve, and a discontinuous curve, and wherein the seal ring is substantially aligned with a periphery of the active circuit region.
4. The method of claim 1 , wherein the seal ring is a continuous metallic feature surrounding the active circuit region.
5. The method of claim 1 , wherein the forming the plurality of interconnect metal features in the active circuit region and the forming the seal ring are performed through a common processing flow.
6. The method of claim 1 , wherein the one or more conductive materials is selected from the group consisting essentially of copper, tungsten, aluminum, cobalt, gold, silver, platinum, silicon and combinations thereof.
7. The method of claim 1 further comprising:
forming a first insulating layer over the one or more IMD layers;
forming a first dielectric layer on the first insulating layer; and
forming a first bonding contact on the first dielectric layer, wherein the first bonding contact is coupled to the TSV and to at least one of the plurality of interconnect metal features through a redistribution features in the first insulating layer.
8. The method of claim 7 further comprising:
forming a second insulating layer on a back-side surface of the semiconductor die;
forming a second dielectric layer on the second insulating layer; and
forming a second bonding contact on the second dielectric layer, wherein the second bonding contact is coupled to a second TSVs through a second redistribution feature in the second insulating layer.
9. The method of claim 7 further comprising:
bonding the first semiconductor die to a second semiconductor die through the first bonding contact on the first semiconductor die and a corresponding bonding contact on the second semiconductor die.
10. A method of forming through-silicon-vias (TSV) in a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming one or more inter-metal dielectric (IMD) layers on the semiconductor substrate;
forming one or more semiconductor devices in an active circuit region of the semiconductor substrate;
forming a plurality of interconnect metal features in the IMD layers in the active circuit region;
forming a seal ring in the IMD layers, the seal ring enclosing the plurality of interconnect metal features in the active circuit region;
forming one or more recesses in a TSV region of the IMD layers and the semiconductor substrate, the TSV region being separated from active circuit region by the seal ring; and
filling the one or more recesses with one or more conductive materials, thereby forming one or more TSVs.
11. The method of claim 10 , wherein the seal ring comprises a plurality of stacked metal rings in the one or more IMD layers, the stacked metal rings being connected together through one or more via rings in the one or more IMD layers.
12. The method of claim 10 , wherein the forming the active circuit region and the forming the seal ring are performed through a common processing flow, prior to the forming the one or more recesses in the one or more IMD layers in the TSV region.
13. The method of claim 10 , wherein forming a seal ring comprises forming a plurality of stacked ring features in respective ones of the IMD layers and interconnecting the stacked ring features with a plurality of stacked via structures.
14. The method of claim 10 , wherein the forming the one or more recesses is performed at least in part by a first etching process removing the one or more IMD layers, followed by a second etch process etching the semiconductor substrate.