Method of eliminating micro-trenches during spacer etch

1. A method of forming a semiconductor structure comprising:

providing a semiconductor substrate with a substrate region, the substrate region having an even surface;

forming a pad oxide layer overlying the substrate region;

forming a stop layer overlying the pad oxide layer;

patterning the stop layer and the pad oxide layer to expose a portion of the substrate region;

forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height;

depositing an oxide layer to a first height within the trench using an HDP-CVD process;

depositing a silicon nitride layer within the trench, the silicon nitride layer overlying the oxide layer and at least filling the trench;

performing a planarization process to remove a portion of the silicon nitride and oxide layers to expose a top surface of the trench; and

removing the pad oxide and stop layers;

wherein the top surface of the trench is coplanar with the even surface of the substrate region, and

wherein the planarized silicon nitride layer entirely covers the top surface of the trench.

2. The method of claim 1 further comprising forming a trench liner within the trench, the trench liner lining the sidewalls and the bottom of the trench.

3. The method of claim 1 wherein the first height is up to 80% of the height of the trench.

4. The method of claim 1 wherein the thickness of the oxide layer is between 1000-5000 Å.

5. The method of claim 1 wherein the thickness of the silicon nitride layer is greater than or equal to 1200 Å.

6. The method of claim 1 wherein the silicon nitride layer increases the etch selectivity of the layers overlying the substrate region.

7. The method of claim 1 wherein the planarization process is stopped at the stop layer.

8. A method of forming a semiconductor structure comprising:

providing a semiconductor substrate with a substrate region;

forming a pad oxide layer overlying the substrate region;

forming a stop layer overlying the pad oxide layer;

patterning the stop layer and the pad oxide layer to expose a portion of the substrate region;

forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height;

depositing alternating layers of silicon nitride and oxide to at least fill the trench, the oxide layers being deposited by an HDP-CVD process, and the silicon nitride layer being the top layer;

performing a planarization process to remove a portion of the silicon nitride and oxide layers to expose a top surface of the trench; and

removing the pad oxide and stop layers;

wherein the planarized silicon nitride layer covers entirely the top surface of the trench.

9. The method of claim 7 further comprising forming a trench liner within the trench, the trench liner lining the sidewalls and the bottom of the trench.

10. The method of claim 7 further comprising forming an additional layer of oxide overlying the alternating layers of silicon nitride and oxide.

11. The method of claim 10 wherein the additional layer of oxide has a thickness between 500-1500 Å.

12. The method of claim 7 wherein the planarization process is stopped at the stop layer.

13. The method of claim 7 wherein the alternating layers of silicon nitride and oxide increase the etch selectivity of the layers overlying the substrate region.

14. The method of claim 7 wherein the thickness of the oxide layer is between 50-1000 Å.

15. The method of claim 7 wherein the thickness of the silicon nitride layer is between 200-3000 Å.

16. The method of claim 7 wherein process conditions used in the depositing alternating layers of silicon nitride and oxide may be set to control the stress of a silicon channel.