IP Library Granted Patent US 8,202,803
Granted Patent B2
US 8,202,803 · App. 12/636,430 · Granted Jun 19, 2012

Method to remove capping layer of insulation dielectric in interconnect structures

Assignee: Tokyo Electron Limited
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,202,803
App. No.
12/636,430
Granted
Jun 19, 2012
Kind
B2
Abstract

A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.

Claims (26)

1. A method of preparing an insulating film on a substrate, comprising:

disposing a substrate having an insulation layer and a cap layer overlying said insulation layer in a treatment system, wherein a pattern has been transferred to said cap layer and said insulation layer in order to form a feature through said cap layer and within said insulation layer, and wherein a surface layer of said insulation layer has been exposed to an etching plasma during said pattern transfer to said insulation layer;

filling said feature in said insulation layer with organic material prior to metalizing said feature;

following said filling said feature in said insulation layer with organic material, removing said cap layer using a dry non-plasma etching process, wherein said dry non-plasma etching process comprises:

exposing at least a portion of said cap layer to a process gas comprising HF or NH 3 or a combination thereof in order to chemically alter said cap layer, and

thermally treating said chemically altered portion of said cap layer in order to desorb said chemically altered surface portion of said cap layer;

removing said organic material following said performing said dry non-plasma etching process on said cap layer;

performing another dry non-plasma etching process on said insulation layer to remove at least a portion of said exposed surface layer of said insulation layer by:

exposing said exposed surface layer of said insulation layer to a process gas comprising HF or NH 3 or a combination thereof in order to chemically alter said exposed surface layer of said insulation layer, and

thermally treating said chemically altered exposed surface layer of said insulation layer in order to desorb said chemically altered surface layer.

2. The method of claim 1 , wherein said dry non-plasma etching process comprises a self-limiting removal process.

3. The method of claim 1 , wherein said organic material is applied using a spin coating process.

4. The method of claim 1 , wherein said insulation layer comprises a low-k dielectric layer having a dielectric constant less than a value of 4.

5. The method of claim 4 , wherein said low-k dielectric layer has a dielectric constant ranging from 1.6 to 2.7.

6. The method of claim 4 , wherein said low-k dielectric layer comprises: a cured low-k dielectric material; an uncured low-k dielectric material; an organic material; an inorganic material; an inorganic-organic hybrid material; a porous dielectric material; a non-porous dielectric material; a single-phase material; a dual-phase material; an oxidized organo silane material; a silsesquioxane material; a silicate-based material; a collective material including silicon, carbon, and oxygen; or a collective material including silicon, carbon, oxygen, and hydrogen; or any combination of two or more thereof.

7. The method of claim 1 , wherein said exposing said portion of said cap layer to said process gas causes chemical alteration of said cap layer to a self-limiting depth, and wherein said chemically altered portion of said cap layer to said self-limiting depth is removed during said thermal treating.

8. The method of claim 1 , wherein said exposing said cap layer is performed at a process pressure ranging from approximately 1 mtorr to approximately 100 torr while said substrate is at a temperature ranging from approximately 10 degrees C. to approximately 200 degrees C.

9. The method of claim 1 , wherein said process gas further comprises a noble gas.

10. The method of claim 1 , wherein said thermally treating said chemically altered portion of said cap layer comprises elevating a temperature of said substrate to above approximately 100 degrees C.

11. The method of claim 10 , wherein said thermally treating said chemically altered portion of said cap layer is performed during introducing a noble gas or nitrogen.

12. The method of claim 1 , wherein said cap layer comprises silicon oxide (Si x O y ), silicon nitride (Si x N y ), silicon oxynitride (Si x O y N z ), or silicon oxycarbide (Si x O y C z ), or any combination of two or more thereof.

13. The method of claim 1 , wherein said process gas comprises HF and NH 3 , wherein said HF and NH 3 are introduced to said treatment system independent of one another.

14. The method of claim 1 , wherein said process gas comprises NH 3 , or NH 3 and a noble gas.

15. The method of claim 1 , further comprising:

repeating said exposing said cap layer to said process gas and said thermally treating said chemically altered portion of said cap layer until said cap layer is removed.

16. The method of claim 1 , wherein said feature comprises a trench, or a via, or a combination thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2009
From: FEURPRIER, YANNICK; TRICKETT, DOUGLAS M.
To: TOKYO ELECTRON LIMITED
Reel/Frame 023643/0910 →
Continuity (1)
Related Publication 20110143542A1 · Jun 16, 2011