Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verification
A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, and each of the trace status tables contains a trace error identified by a formal verification engine that was utilized to perform a relative timing (RT) verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.
1. A computer system for automatically synthesizing relative timing (RT) constraints for facilitating timing verifications of an integrated circuit design, said computer system comprising:
means for receiving a plurality of trace status tables containing a plurality of trace errors identified by a formal verification engine that performed an RT verification on an integrated circuit design;
means for identifying an error causing signal for each of said trace errors;
for each of error causing signals,
means for determining two associating signals;
means for utilizing said two associating signals to locate a common point of convergence (POC);
means for backtracking said POC to locate a common point of divergence (POD); and
means for generating an RT constraint based on said POC and POD; and
means for inserting an RT constraint for each of said trace errors within said integrated circuit design, wherein said RT constraints specify the relative ordering of arrivals of signals in order to avoid any timing violations such that said integrated circuit design is able to pass said RT verification in the future.
2. The computer system of claim 1 , wherein said integrated circuit design is an asynchoronous integrated circuit design.
3. The computer system of claim 1 , wherein said RT verification is an unbound verification.
4. The computer system of claim 1 , wherein said error causing signal is an input signal.
5. The computer system of claim 1 , wherein said error causing signal is an output signal.