IP Library Granted Patent US 8,242,564
Granted Patent B2
US 8,242,564 · App. 13/313,806 · Granted Aug 14, 2012

Semiconductor device with photonics

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,242,564
App. No.
13/313,806
Granted
Aug 14, 2012
Kind
B2
Abstract

A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.

Claims (46)

1. A semiconductor structure, comprising:

a substrate;

a first insulating layer over the substrate;

in a transistor region, a first semiconductor layer over the first insulating layer, a second insulating layer over the first semiconductor layer, a second semiconductor layer over the second insulating layer, and a transistor having a gate dielectric, the gate dielectric over and in physical contact with a top surface of the second semiconductor layer, wherein the first semiconductor layer has a bottom surface and a top surface opposite the bottom surface, and wherein the top surface of the first semiconductor layer is between the bottom surface of the first semiconductor layer and the second insulating layer; and

in an optical device region, a waveguide device over the first insulating layer, wherein the waveguide device has a bottom surface and a top surface opposite the bottom surface, wherein the bottom surface of the waveguide device is substantially coplanar with the bottom surface of the first semiconductor layer, wherein the top surface of the waveguide device has a first portion and a second portion, the second portion being located higher than the first portion with respect to the bottom surface of the waveguide device, wherein the waveguide device comprises a continuous semiconductor material, wherein the second portion of the top surface of the waveguide device is substantially coplanar with the top surface of the second semiconductor layer, and wherein the continuous semiconductor material is epitaxially grown on the second portion.

2. The semiconductor structure of claim 1 , wherein the first portion of the top surface of the waveguide device is substantially coplanar with the top surface of the first semiconductor layer.

3. The semiconductor structure of claim 1 , further comprising an isolation region between the transistor region and optical device region, the isolation region extending to the first insulating layer.

4. The semiconductor structure of claim 1 , further comprising a photodetector over and in physical contact with the second portion of the top surface of the waveguide device.

5. A semiconductor structure having a transistor region and an optical device region, comprising:

a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure; and

a waveguide device in the optical device region of the semiconductor structure, wherein the waveguide device includes a third semiconductor layer epitaxially grown over a portion of the second semiconductor layer in the optical device region.

6. The structure of claim 5 , wherein portions of the first semiconductor layer and the first insulating layer are removed in the optical device region over the portion of the second semiconductor layer.

7. The structure of claim 6 , wherein the waveguide device further comprises:

an opening in the third semiconductor layer that defines a top surface of the waveguide device having a higher portion and a lower portion, wherein the higher portion of the top surface of the waveguide device is higher than the lower portion of the top surface of the waveguide device with respect to the second semiconductor layer.

8. The structure of claim 7 , further comprising:

the opening in the third semiconductor layer is filled with an insulating material.

9. The structure of claim 7 , further comprising:

openings in the first semiconductor layer in the transistor region, wherein the openings are formed prior to forming the transistor.

10. The structure of claim 9 , further comprising:

the openings in the first semiconductor layer and the opening in the third semiconductor layer are filled with an insulating material.

11. The structure of claim 5 , wherein a top surface of the third semiconductor layer is substantially coplanar with the top surface of the first semiconductor layer.

12. The structure of claim 5 , further comprising:

an isolation region formed between the transistor region and the optical device region, wherein the isolation region extends to the second insulating layer.

13. The structure of claim 5 , further comprising:

a photodetector formed over and in physical contact with the waveguide device.

14. The structure of claim 5 , further comprising:

an opening in the optical device region filled with a third insulating layer.

15. The structure of claim 14 , wherein:

portions of the third insulating layer in the optical device region and the first insulating layer in the optical device region are removed to expose the portion of the second semiconductor layer.

16. The structure of claim 14 , further comprising:

openings formed in the first semiconductor layer in the transistor region and the first semiconductor layer is removed in the optical device region.

17. The structure of claim 16 , further comprising:

the openings in the first semiconductor layer are filled with an insulating material.

18. The structure of claim 5 , wherein, prior to the exposing the portion of the second semiconductor layer, the forming the waveguide device further comprises:

removing the first semiconductor layer in the optical device region and the first insulating layer in the optical device region, resulting in an opening; and

filling the opening with a third insulating layer;

wherein the exposing the portion of the second semiconductor layer comprises:

removing portions of the third insulating layer in the optical device region to expose the portion of the second semiconductor layer.

19. A semiconductor structure having a transistor region and an optical device region, comprising:

an isolation region between the transistor region and the optical device region;

a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, wherein the transistor is formed in the transistor region, and wherein the isolation region extends to the second insulating layer; and

a waveguide device in the optical device region of the semiconductor structure, wherein the waveguide device comprises:

an opening in the first semiconductor layer in the optical device region;

a third insulating layer filling the opening in the first semiconductor layer; and

a third semiconductor layer over the portion of the second semiconductor layer.

20. The structure of claim 19 , wherein a top surface of the third semiconductor layer is substantially coplanar with the top surface of the first semiconductor layer.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0379 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0447 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0439 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027821/0967 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027821/0662 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027821/0982 →