Method and resulting structure for deep trench polysilicon hard mask removal

1. A method of forming a capacitor structure for a dynamic random access memory integrated circuit, the method comprising:

providing a semiconductor substrate;

forming a pad oxide layer overlying the semiconductor substrate;

forming a nitride layer overlying the pad oxide layer;

forming an interlayer dielectric layer overlying the nitride layer;

forming a polysilicon mask layer overlying the interlayer dielectric layer;

patterning the polysilicon mask layer to form an opening therein for a trench structure;

applying a first reactive ion etching process to form a first trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer;

maintaining the first reactive ion etching process to etch through a portion of the nitride layer and through a portion of the pad oxide layer;

ceasing the first reactive ion etching process when a surface region of the semiconductor substrate has been exposed;

forming an oxide layer overlying the surface region of the semiconductor substrate to protect the surface region of the semiconductor substrate;

removing the patterned polysilicon mask layer while protecting the surface region of the semiconductor substrate using the oxide layer;

applying a second reactive ion etching process to continue to form a second trench region by removing the oxide layer and removing a portion of the semiconductor substrate to a predetermined depth in the semiconductor substrate;

forming a lower electrode plate overlying at least a portion of the first trench region and the entire second trench region;

forming a dielectric layer overlying the lower electrode plate; and

forming an upper electrode plate to complete the capacitor structure.

2. The method of claim 1 wherein the forming an oxide layer comprises the use of an O 2 bearing gas species at about 270 degrees Celsius.

3. The method of claim 2 wherein the oxide layer comprises a thickness of 30 Angstroms and less.

4. The method of claim 1 wherein the trench region within the interlayer dielectric layer comprises a width of 0.15 micron and a depth of about 2 microns and more.

5. The method of claim 4 wherein the trench region through the interlayer dielectric layer and through the portion of the semiconductor substrate comprises a length of 8 microns and more.

6. The method of claim 1 wherein the first reactive ion etching process uses C 4 F 8 and C 3 F 6 species.

7. The method of claim 1 wherein the second reactive ion etching process uses HF3 and HBr bearing species.

8. The method of claim 1 further comprising a wet cleaning process after ceasing the first reactive ion etching process and before forming the oxide layer.

9. The method of claim 1 further comprising forming a bottom electrode to line an interior region of the trench structure.

10. The method of claim 1 wherein the oxide layer comprises a silicon dioxide material.

11. The method of claim 1 wherein the second trench region in the semiconductor substrate is free from a mechanical damage.

12. The method of claim 1 wherein the second trench region comprises sidewalls that are substantially vertical.

13. The method of claim 1 wherein the second trench region is free from mechanical imperfections.

14. The method of claim 1 wherein the forming a lower electrode plate comprising in-situ doping with a phosphorous species.

15. The method of claim 1 wherein the dielectric layer comprises a silicon nitride material having a dielectric constant of about 7.

16. The method of claim 1 further comprising:

forming a polysilicon layer over the first and second trench regions, the polysilicon layer being doped with an arsenic species; and

diffusing the arsenic species through annealing.

17. The method of claim 1 further comprising providing a hemispherical grain silicon layer overlying the lower electrode plate.

18. The method of claim 1 wherein the ceasing the first reactive ion etching process comprises an end point detection process.