Display apparatus and driver

1. A display apparatus comprising:

a display section;

M latching sections (M is a multiple of 3 or 2) configured to receive and hold display data to be displayed on said display section, wherein said M latching sections are grouped into Y latching section groups and each of said Y latching section groups comprises X of said M latching sections (Y is an integer equal to or more than 2 and X is an integer which meets M=X×Y);

M input switches respectively connected with outputs of said M latching sections, wherein said M input switches are grouped into Y switch groups, each of said Y input switch groups comprises X of said M input switches, and each of said X input switches of each of said Y input switch groups is turned on in response to an input switching control signal for Y clocks;

Y digital-to-analog (D/A) converters respectively connected with said Y input switch groups, wherein each of said Y D/A converters converts the display data held by each of said X latching sections of a corresponding one of said Y latching section groups into an output gradation voltage;

Y amplifiers configured to amplify and output the output gradation voltages from said Y D/A converters, respectively;

Y output switches provided between outputs of said Y amplifiers and an output node, respectively, wherein each of said Y output switches is turned on in response to an output switching control signal for one clock, and M data lines connected with the output node are provided on said display section;

M data line switches provided onto said M data lines, respectively, wherein each of said M data line switches is turned on in response to a data line switching control signal for one clock; and

a control section configured to sequentially supply said M input switching control signals to said M input switches, sequentially supply said output switching control signals to said Y output switches, and sequentially supplies said M data line switching control signals to said M data line switches in synchronization with a Y th clock of said input switching control signal.

2. The display apparatus according to claim 1 , wherein said display section is applied to a color display of primary colors of red, green and blue, and

when M is a multiple of 3, X is 3 and Y is an integer equal to or more than 2.

3. The display apparatus according to claim 1 , wherein said display section is applied to a color display of primary colors of red, green and blue, and

when M is a multiple of 3, Y is 3 and X is an integer equal to or more than 2.

4. The display apparatus according to claim 1 , wherein said display section is applied to a positive drive and a negative drive in a 2 dot inversion drive,

when M is a multiple of 2, Y is 4 and X is an integer equal to or more than 2,

first and second output switches of said Y output switches are applied to one of the positive drive and the negative drive,

third and fourth output switches of said Y output switches are applied to the other of the positive drive and the negative drive.

5. A driver circuit comprising:

M latching sections (M is a multiple of 3 or 2) configured to receive and hold display data to be displayed on a display section, wherein said M latching sections are grouped into Y latching section groups and each of said Y latching section groups comprises X of said M latching sections (Y is an integer equal to or more than 2 and X is an integer which meets M=X×Y);

M input switches respectively connected with outputs of said M latching sections, wherein said M input switches are grouped into Y input switch groups, each of said Y input switch groups comprises X of said M input switches, and each of said X input switches of each of said Y input switch groups is turned on in response to an input switching control signal for Y clocks;

Y digital-to-analog (D/A) converters respectively connected with said Y input switch groups, wherein each of said Y D/A converters converts the display data held by each of said X latching sections of a corresponding one of said Y latching section groups into an output gradation voltage;

Y amplifiers configured to amplify and output the output gradation voltages from said Y D/A converters, respectively;

Y output switches provided between outputs of said Y amplifiers and an output node, respectively, wherein each of said Y output switches is turned on in response to an output switching control signal for one clock;

wherein M data lines connected with the output node are provided on said display section, and M data line switches are interposed between said M data lines and the output node,

wherein each of said M data line switches is turned on in response to a data line switching control signal for one clock; and

a control section configured to sequentially supply said M input switching control signals to said M input switches, sequentially supply said output switching control signals to said Y output switches, and sequentially supplies said M data line switching control signals to said M data line switches in synchronization with a Y th clock of said input switching control signal.

6. The driver circuit according to claim 5 , wherein said display section is applied to a color display of primary colors of red, green and blue, and

when M is a multiple of 3, X is 3 and Y is an integer equal to or more than 2.

7. The driver circuit according to claim 5 , wherein said display section is applied to a color display of primary colors of red, green and blue, and

when M is a multiple of 3, Y is 3 and X is an integer equal to or more than 2.

8. The driver circuit according to claim 5 , wherein said display section is applied to a positive drive and a negative drive in a 2 dot inversion drive,

when M is a multiple of 2, Y is 4 and X is an integer equal to or more than 2,

first and second output switches of said Y output switches are applied to one of the positive drive and the negative drive,

third and fourth output switches of said Y output switches are applied to the other of the positive drive and the negative drive.