Single instruction decode circuit for decoding instruction from memory and instructions from an instruction generation circuit
View Patent ↗A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit.
1. A processor comprising:
a plurality of registers;
an instruction readout circuit configured to read out an instruction from a memory;
an instruction decode circuit configured to decode the instruction read out from the memory by the instruction readout circuit;
an instruction generation circuit configured to generate instructions, each for saving data of a respective one of the plurality of registers into a predetermined storage area, if the instruction read out from the memory by the instruction readout circuit and decoded by the instruction decode circuit is an instruction causing the data stored in each of the plurality of registers to be saved;
an address calculation circuit; and
a data memory interface;
the instruction decode circuit being further configured to decode the instructions generated by the instruction generation circuit;
the address calculation circuit being configured to calculate an address within the predetermined storage area based on a decode result of the instruction decode circuit;
the data memory interface being configured to access the predetermined storage area based on the address calculated by the address calculation circuit.
2. The processor of claim 1 , wherein
the instruction generation circuit is further configured to generate instructions, each for restoring the data from the predetermined storage area into the respective one of the plurality of registers, if the instruction read out from the memory by the instruction readout circuit and decoded by the instruction decode circuit is an instruction causing the data saved in the predetermined storage area to be restored in each of the plurality of registers.
3. The processor of claim 2 , further comprising
a control circuit configured to instruct the instruction generation circuit to generate the instructions for the respective registers as well as the instruction readout circuit to stop reading out the instruction from the memory, if the instruction read out from the memory by the instruction readout circuit and decoded by the instruction decode circuit is an instruction causing the instruction generation circuit to generate the instructions for the respective registers.
4. The processor of claim 3 , further comprising
a storage circuit configured to store a specification data for specifying a portion of the plurality of registers, wherein
the instruction generation circuit is further configured to generate the instructions for registers respectively, the registers being specified by the specification data stored in the storage circuit among the plurality of registers.
5. The processor of claim 2 , further comprising
a storage circuit configured to store a specification data for specifying a portion of the plurality of registers, wherein
the instruction generation circuit is further configured to generate the instructions for registers respectively, the registers being specified by the specification data stored in the storage circuit among the plurality of registers.
6. The processor of claim 1 , further comprising
a control circuit configured to instruct the instruction generation circuit to generate the instructions for the respective registers as well as the instruction readout circuit to stop reading out the instruction from the memory, if the instruction read out from the memory by the instruction readout circuit and decoded by the instruction decode circuit is an instruction causing the instruction generation circuit to generate the instructions for the respective registers.
7. The processor of claim 6 , further comprising
a storage circuit configured to store a specification data for specifying a portion of the plurality of registers, wherein
the instruction generation circuit is further configured to generate the instructions for registers respectively, the registers being specified by the specification data stored in the storage circuit among the plurality of registers.
8. The processor of claim 1 , further comprising
a storage circuit configured to store a specification data for specifying a portion of the plurality of registers, wherein
the instruction generation circuit is further configured to generate the instructions for registers respectively, the registers being specified by the specification data stored in the storage circuit among the plurality of registers.