Semiconductor package and multichip arrangement having a polymer layer and an encapsulant
A polymer layer is generated on a wafer. The wafer is then separated into semiconductor chips. At least two semiconductor chips are placed on a carrier with the polymer layer facing the carrier. The at least two semiconductor chips are covered with an encapsulating material to form an encapsulant. The carrier is removed from the encapsulant, and the encapsulant and the polymer layer are thinned.
1. A semiconductor device, comprising:
a semiconductor chip having a first main chip surface and a second main chip surface;
a polymer layer arranged over the first main chip surface; and
an encapsulant made of molding material accommodating the semiconductor chip, the encapsulant having a first mold surface and a second mold surface, wherein
the first mold surface and a surface of the polymer layer facing away from the semiconductor chip form a common planar surface, wherein the polymer layer comprises a photosensitive material.
2. A semiconductor device comprising:
a semiconductor chip having a first main chip surface and a second main chip surface;
a polymer layer arranged over the first main chip surface; and
an encapsulant made of molding material accommodating the semiconductor chip, the encapsulant having a first mold surface and a second mold surface, wherein the first mold surface and a surface of the polymer layer facing away from the semiconductor chip form a common planar surface, wherein the encapsulant comprises an epoxy material.
3. A semiconductor device comprising:
a semiconductor chip having a first main chip surface and a second main chip surface;
a polymer layer arranged over the first main chip surface; and
an encapsulant made of molding material accommodating the semiconductor chip, the encapsulant having a first mold surface and a second mold surface, wherein the first mold surface and a surface of the polymer layer facing away from the semiconductor chip form a common planar surface, wherein the common planar surface has maximum step-like height variations of less than 1000 nm.
4. The semiconductor device of claim 1 , further comprising a layer of conductive material overlying the common planar surface.
5. The semiconductor device of claim 4 , wherein the layer of conductive material is electrically connected to a contact pad on the semiconductor chip through an opening in the polymer layer.
6. The semiconductor device of claim 4 , further comprising a layer of insulating material overlying the layer of conductive material.
7. The semiconductor device of claim 6 , wherein the layer of insulating material comprises openings configured as solder stops.
8. The semiconductor device of claim 4 , further comprising solder depots attached to the layer of conductive material.
9. The semiconductor device of claim 1 wherein the polymer layer is filled with a filler material, comprising mineral or organic particles.
10. A sheet-like multichip arrangement, comprising:
an array of semiconductor chips, each semiconductor chip having a first main chip surface and a second main chip surface;
polymer layers arranged over the first main chip surfaces; and
an encapsulant made of molding material accommodating the semiconductor chips, the encapsulant having a first mold surface and a second mold surface, wherein the first mold surface and surfaces of the polymer layers facing away from the semiconductor chips form a common planar surface of the multichip arrangement, wherein the common planar surface of the multichip arrangement has step-like height variations.
11. The sheet-like multichip arrangement of claim 10 , the common planar surface of the multichip arrangement has maximum step-like height variations of less than 1000 nm.
12. A semiconductor device, comprising:
a semiconductor chip having a first main chip surface and a second main chip surface;
a polymer layer arranged over the first main chip surface; and
an encapsulant made of molding material accommodating the semiconductor chip, the encapsulant having a first mold surface and a second mold surface, wherein the first mold surface and a surface of the polymer layer facing away from the semiconductor chip form a common planar surface, wherein the polymer layer is filled with a filler material comprising mineral or organic particles.
13. The semiconductor device of claim 12 , further comprising a layer of conductive material overlying the common planar surface.
14. The semiconductor device of claim 13 , wherein the layer of conductive material is electrically connected to a contact pad on the semiconductor chip through an opening in the polymer layer.
15. The semiconductor device of claim 13 , further comprising a layer of insulating material overlying the layer of conductive material.
16. The semiconductor device of claim 15 , wherein the layer of insulating material comprises openings configured as solder stops.
17. The semiconductor device of claim 13 , further comprising solder depots attached to the layer of conductive material.
18. The semiconductor device of claim 12 , wherein the common planar surface has step-like height variations.
19. The semiconductor device of claim 12 , wherein the common planar surface has maximum step-like height variations of less than 1000 nm.