Circuit board viaholes and method of manufacturing the same
View Patent ↗Provided are a circuit board with a viahole and a method of manufacturing the same. The circuit board includes: a substrate formed of an insulating material; a conductive layer disposed on the substrate; a plated layer comprising nickel and disposed on the conductive layer; and a viahole passing through the substrate, the conductive layer, and the plated layer, wherein a crystal growth direction of nickel in the plated layer is parallel to a thickness-wise direction of the substrate.
1. A viahole, the viahole formed through a circuit board, the circuit board comprising
a conductive layer formed on a substrate of the circuit board; and
a layer of nickel crystals formed directly on the conductive layer,
wherein the nickel crystals of the layer of nickel crystals are grown substantially parallel to a depth-wise direction of the viahole; and wherein a surface roughness (Ra) of the layer of the nickel crystals ranges from 0.4 μm to 0.6 μm and is greater than a surface roughness of the conductive layer.
2. The viahole of claim 1 , wherein a gloss degree of the layer of nickel crystals is in a range of 0.5 to 2.
3. The viahole of claim 1 , wherein the viahole is formed using a CO 2 laser.
4. The viahole of claim 1 , wherein the layer of nickel crystals is grown by providing a current of 10 ASD (A/dm 2 ) to 30 ASD (A/dm 2 ) to the conductive layer.
5. The viahole of claim 4 , wherein the layer of nickel crystals is grown by providing the current for 3 seconds to 20 seconds to the conductive layer.
6. A viahole, the viahole formed through a circuit board, the circuit board comprising
a conductive layer formed on a substrate of the circuit board; and
a layer of nickel crystals formed directly on the conductive layer,
wherein the nickel crystals of the layer of nickel crystals have a crystal growth direction substantially parallel to a depth-wise direction of the viahole; and wherein a surface roughness (Ra) of the layer of the nickel crystals ranges from 0.4 μm to 0.6 μm and is greater than a surface roughness of the conductive layer.