Anti-fuse based programmable serial number generator
View Patent ↗An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.
1. An integrated circuit apparatus, comprising:
a semiconductor substrate, the substrate being characterized by a first conductivity type;
a well region within the semiconductor substrate, the well region being characterized by a second conductivity type, a junction between the well region and the substrate being characterized by a breakdown voltage higher than a predetermined voltage;
a plurality of isolation regions;
a contact region within the well region, the contact region being characterized by the second conductivity type, the contact region being configured to receive a first supply voltage;
a channel region within the substrate;
a drain region, the drain region being characterized by the second conductivity type, the drain region being separated from the well region by the channel region;
a gate dielectric layer overlying the channel region and the contact region;
a first polysilicon gate overlying the gate dielectric layer which overlies the channel region, an edge of the first polysilicon gate overlying a portion of the well region, the first polysilicon gate, the drain region, and the well region being associated with a gate region, a drain region, and a source region, respectively, of an MOS transistor; and
a second polysilicon gate overlying the gate dielectric layer which overlies the contact region, the second polysilicon gate being configured to receive a second supply voltage.
2. The apparatus of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
3. The apparatus of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type, and wherein the first supply voltage is higher than the second supply voltage.
4. The apparatus of claim 1 , wherein the well region is characterized by a depth of more than 1 um.
5. The apparatus of claim 1 , wherein the well region is characterized by a depth of more than 0.5 um.
6. The apparatus of claim 1 , wherein the predetermined voltage is higher than a breakdown voltage of the gate dielectric.
7. The apparatus of claim 1 , wherein the predetermined voltage is about 10-15 volts.
8. The apparatus of claim 1 , wherein a voltage difference between the first supply voltage and the second supply voltage is greater than a breakdown voltage of the gate dielectric layer.
9. An integrated circuit apparatus, the apparatus comprising:
a semiconductor substrate comprising a surface region, the substrate being characterized by a first conductivity type;
a first well region within the semiconductor substrate, the first well region being characterized by a second conductivity type;
a second well region within the semiconductor substrate, the second well region being characterized by the second conductivity type, a junction between the second well region and the substrate being characterized by a breakdown voltage higher than a predetermined voltage;
a third well region within the semiconductor substrate, the third well region being characterized by the first conductivity type;
a plurality of isolation regions;
a gate dielectric layer overlying the surface region overlying the substrate, the first well region, second well region, and the third well region;
first MOS transistor comprising a drain region and a source region within the third well region, the first transistor further comprising a first gate overlying the gate dielectric;
second MOS transistor comprising a drain region and a source region within the first well region, the second MOS transistor further comprising a second gate overlying the gate dielectric;
a sense transistor comprising a drain region within the substrate and a gate overlying a portion of the second well region, the second well region being configured as a source for the sense transistor; and
an anti-fuse memory device comprising a contact region within the second well region, the contact region being characterized by the second conductivity type, the contact region being also characterized by a higher conductivity than the well region, the anti-fuse memory device further comprising a gate electrode overlying the gate dielectric, the gate electrode also overlying a portion of the contact region.
10. The apparatus of claim 9 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
11. The apparatus of claim 9 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
12. The apparatus of claim 9 , wherein the second well region is characterized by a depth of more than 1 um.
13. The apparatus of claim 9 , wherein the predetermined voltage is higher than a breakdown voltage of the gate dielectric.
14. The apparatus of claim 9 , wherein the predetermined voltage is about 10-15 volts.