IP Library Granted Patent US 8,357,974
Granted Patent B2
US 8,357,974 · App. 12/827,582 · Granted Jan 22, 2013

Semiconductor on glass substrate with stiffening layer and process of making the same

Inventors: Nadia Ben Mohamed (Ech/Rolls, FR); Ta Ko Chuang (Painted Post, NY); Jeffrey Scott Cites (Horseheads, NY); Daniel Delprat (Crolles, FR); Alex Usenko (Painted Post, NY)
Assignees: Corning Incorporated; SOITEC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,357,974
App. No.
12/827,582
Granted
Jan 22, 2013
Kind
B2
Abstract

A semiconductor-on-glass substrate having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer or layers placed between the silicon film and the glass in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the ion implantation thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.

Claims (24)

1. A semiconductor on glass structure, comprising:

a glass substrate;

a stiffening layer having a Young's modulus of about 125 GPa or higher on the glass substrate;

an oxide layer on the stiffening layer; and

a semiconductor layer on the oxide layer, the semiconductor layer having a surface roughness with a skewness level of about 0.6 or lower.

2. The semiconductor on glass structure of claim 1 , wherein an exposed surface of the semiconductor layer has a surface roughness with a skewness level of about 0.4 or lower.

3. The semiconductor on glass structure of claim 2 , wherein the exposed surface of the semiconductor layer has a surface roughness of about 2 nm RMS or less.

4. The semiconductor on glass structure of claim 1 , wherein the stiffening layer has a thickness about 50 nm or greater.

5. The semiconductor on glass structure of claim 4 , wherein the stiffening layer is formed of Si 3 N 4 .

6. The semiconductor on grass structure of claim 1 , wherein the oxide layer is a SiO 2 layer on having a thickness of about 2 nm to about 150 nm.

7. The semiconductor on glass structure of claim 1 , wherein the semiconductor wafer is formed of substantially single crystal silicon and further comprising a SiO 2 layer with a thickness within the range from about 1 nm to about 10 nm or less, or from about 2 nm to about 5 nm, of about 20 nm or less, of about 10 nm or less, about 7 nm or less, or about 100 nm or less between the semiconductor wafer and the stiffening layer; and

wherein the glass substrate includes (i) a first glass layer adjacent to the exfoliation layer in which substantially no modifier positive ions are present, and (ii) a second glass layer adjacent the first glass layer having an enhanced concentration of modifier positive ions.

8. The semiconductor on glass structure of claim 1 , wherein the stiffening layer has a Young's modulus of about 150 GPa or higher.

9. The semiconductor on glass structure of claim 8 , wherein the stiffening layer has a Young's modulus of about 200 GPa or higher.

10. The semiconductor on glass structure of claim 9 , wherein the stiffening layer has a Young's modulus of about 300 GPa.

11. The semiconductor on glass structure of claim 2 , wherein the exposed surface of the semiconductor layer has a surface roughness with a skewness level about 0.2 or lower.

12. The semiconductor on glass structure of claim 3 , wherein the exposed surface of the semiconductor layer has a surface roughness of about 1.5 nm RMS or less.

13. The semiconductor on glass structure of claim 12 , wherein the exposed surface of the semiconductor layer has a surface roughness of about or 1 nm RMS or less.

14. The semiconductor on glass structure of claim 4 , wherein the stiffening layer has a thickness of about 100 nm or greater.

15. The semiconductor on glass structure of claim 14 , wherein the stiffening layer has a thickness of about 250 nm or greater.

16. The semiconductor on glass structure of claim 15 , wherein the stiffening layer has a thickness of about 350 nm or greater.

17. The semiconductor on glass structure of claim 6 , wherein the oxide layer has a thickness of about 5 nm to about 150 nm.

18. The semiconductor on glass structure of claim 6 , wherein the oxide layer has a thickness of about 2 nm to about 20 nm.

19. The semiconductor on glass structure of claim 18 , wherein the oxide layer has a thickness of about 5 nm to about 10 nm.

Assignments (2)
CHANGE OF NAME Recorded Oct 12, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 029120/0661 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2010
From: MOHAMED, NADIA BEN; CHUANG, TA KO; CITES, JEFFREY SCOTT; DELPRAT, DANIEL; USENKO, ALEX
To: CORNING INCORPORATED; S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 024984/0851 →
Continuity (1)
Related Publication 20120001293A1 · Jan 5, 2012