Method and device for CMOS image sensing with multiple gate oxide thicknesses
View Patent ↗A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer with at least a first part and a second part on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first part of the gate oxide layer is associated with a first thickness, and the second part of the gate oxide layer is associated with a second thickness. The first thickness and the second thickness are different. The first gate region is located on the first part of the gate oxide layer associated with the first thickness, while the second gate region is located on both the first part of the gate oxide layer associated with the first thickness and the second part of the gate oxide layer associated with the second thickness. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.
1. A method for making an image sensor, the method comprising:
forming a first well and a second well in a substrate;
forming a gate oxide layer including at least a first part and a second part on the substrate, the first part being associated with a first thickness, the second part being associated with a second thickness;
depositing a first gate region and a second gate region on the gate oxide layer, the first gate region being associated with the first well, the second gate region being associated with the second well; and
forming a third well in the substrate;
wherein:
the first well and the second well are associated with a CMOS;
the third well is associated with a photodiode;
the first gate region is located on the first part associated with the first thickness;
the second gate region is located on the first part associated with the first thickness and the second part associated with the second thickness; and
the first thickness and the second thickness are different.
2. The method of claim 1 , wherein the first gate region is not located on the second part associated with the second thickness.
3. The method of claim 2 , wherein the first thickness is less than the second thickness.
4. The method of claim 2 , wherein the third well is located under the second part associated with the second thickness.
5. The method of claim 1 , wherein a source associated with the CMOS is substantially self-aligned with the second gate region.
6. The method of claim 1 , wherein the depositing the first gate region and the second gate region comprises:
depositing a polysilicon layer on the gate oxide layer; and
removing at least a part of the polysilicon layer to form the first gate region and the second gate region.
7. The method of claim 1 , wherein:
the first well is associated with n-type conductivity; and
the second well and the third well each are associated with p-type conductivity.
8. The method of claim 1 , wherein the third well is a source region of an MOS transistor associated with the second well region.
9. The method of claim 8 , wherein the third well is separated from the second well.
10. The method of claim 8 , wherein the third well overlaps with the second well.
11. The method of claim 1 , wherein the first well is characterized by a n-type conductivity, the second well is characterized by a p-type conductivity, and the third well is characterized by an n-type conductivity.