Semiconductor integrated circuit device

1. A semiconductor integrated circuit device comprising:

a group of wirings routed at first to Nth (N being an integer not less than two) wiring positions sequentially disposed in parallel, each of the wirings being divided into two portions comprising a starting end side and a terminating end side; and

an Mth buffer circuit that connects the starting end side of the wiring at the Mth wiring position (M being an integer that satisfies 1≦M≦K, wherein K is an integer that satisfies K≦N/2) as an input and the terminating end side of the wiring at the (M+N−K)th wiring position as an output;

wherein said group of the wirings has a structure in which connection is switched so that the starting end side of the wiring at a Jth (J being an integer. that satisfies K<J≦N) wiring position is routed to the terminating end side of the wiring at a (J−K)th wiring position on a wiring layer above a placement region of the buffer circuit(s).

2. The semiconductor integrated circuit device according to claim 1 , wherein

the semiconductor integrated circuit device comprises multiple stages of the wirings and the buffer circuit, and the multiple stages are formed by connecting a terminating end side of the wirings and the buffer circuit(s) of one stage to a starting end side of the wirings of a subsequent stage.

3. The semiconductor integrated circuit device according to claim 2 , wherein

N is integer times of K, and a number of the multiple stages is N/K.

4. The semiconductor integrated circuit device according to claim 1 , wherein

the buffer circuit includes an inverter circuit comprising a CMOS structure in which mutually complementary two transistors are formed in a direction of the wiring position(s).

5. The semiconductor integrated circuit device according to claim 4 , wherein

the buffer circuit has a configuration in which two of inverter circuits are disposed adjacent to each other in a direction orthogonal to the direction of the wiring position(s) and the two inverter circuits are connected in series.

6. The semiconductor integrated circuit device according to claim 4 , wherein

the buffer circuit has a configuration in which two of inverter circuits are disposed adjacent to each other in the direction of the wiring position(s) and the two inverter circuits are connected in series.

7. The semiconductor integrated circuit device according to claim 1 , comprising:

a plurality of functional blocks arranged in an array form, the functional blocks having a same structure;

each of the functional blocks including the group of the wirings and the buffer circuit(s) of one stage.

8. The semiconductor integrated circuit device according to claim 7 , wherein

the functional block comprises a memory cell array and a selection circuit that selects a memory cell of the memory cell array; and

the selection circuit includes the group of the wirings and the buffer circuit(s) of one stage.

9. The semiconductor integrated circuit device according to claim 7 , wherein

the functional block comprises memory cell arrays and a control circuit that controls selection of a memory cell of the memory cell arrays; and

the control circuit includes the group of the wirings and the buffer circuit(s) of one stage.