IP Library › Granted Patent US 8,418,356
Granted Patent B2
US 8,418,356 · App. 12/213,704 · Granted Apr 16, 2013

Method of manufacturing an embedded printed circuit board

Inventors: Kwang Soo Park (Busan, KR); Myung Gun Chong (Gyeongsangnam-do, KR); Dek Gin Yang (Chungcheongbuk-do, KR); Dae Jung Byun (Busan, KR)
Assignee: Samsung Electro-Mechanics Co., Ltd.
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Quick Facts
Patent No.
US 8,418,356
App. No.
12/213,704
Granted
Apr 16, 2013
Kind
B2
Abstract

The present invention relates to an embedded printed circuit board and a manufacturing method thereof. The present invention provides an embedded printed circuit board including a substrate in which a cavity is formed in a predetermined portion and a wiring layer is formed in a portion without the cavity; a chip inserted into the cavity and including a plurality of pads; a filler filled between the chip and the cavity to fix the chip; and a connection layer formed between the wiring layer and the pads to connect the wiring layer and the pads to each other. Further, the present invention provides a manufacturing method of the embedded printed circuit board.

Claims (14)

1. A method of manufacturing an embedded printed circuit board, the method comprising:

forming a cavity in a predetermined portion of a substrate with a wiring layer;

attaching an adhesive sheet on one surface of the substrate;

inserting a chip with a plurality of pads into the cavity to fix the inserted chip onto the adhesive sheet;

filling a filler between the cavity and the chip; and

forming a connection layer connected to the wiring layer and the pads only in an area between the wiring layer and one or more of the pads,

wherein a top surface of the chip and a top surface of the filler are in a same horizontal plane, and

wherein the connection layer is formed such that one part of the connection layer is on the top surface of the filler and another part of the connection layer is on the top surface of the chip.

2. The method as recited in claim 1 , wherein the connection layer is connected to a pad positioned in an outermost portion of the chip.

3. The method as recited in claim 1 , wherein the connection layer is horizontally contacted with one lateral surface of the wiring layer and one lateral surface of a pad selected from the pads, and the one lateral surface of the wiring layer and the one lateral surface of the selected pad are directed perpendicular to the substrate.

4. The method as recited in claim 1 , wherein the connection layer is made of copper (Cu) or silver (Ag).

5. The method as recited in claim 1 , wherein the chip is any one selected from a group consisting of an active element, a passive element, and an IC (Integrated Circuit).

6. The method as recited in claim 1 , wherein the chip is an integrated circuit.

7. The method as recited in claim 1 , wherein the connection layer is made by a screen printing method.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2008
From: PARK, KWANG SOO; CHONG, MYUNG GUN; YANG, DEK GIN; BYUN, DAE JUNG
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 021186/0603 →
Priority Claims (1)
KR 10-2008-0027371 · Mar 25, 2008 · national
Continuity (1)
Related Publication 20090242251A1 · Oct 1, 2009